公开(公告)号：US09978116B2

公开(公告)日：2018-05-22

申请号：US15598082

申请日：2017-05-17

Applicant: Google LLC

Inventor： Albert Meixner ,  Daniel Frederic Finchelstein ,  David Patterson ,  William Mark ,  Jason Rupert Redgrave ,  Ofer Shacham

IPC: G06K9/00 ,  G06T1/20 ,  G11C19/28

CPC classification number: G06T1/20 ,  G06K9/00986 ,  G11C19/28

Abstract: A method is described that includes, on an image processor having a two dimensional execution lane array and a two dimensional shift register array, doubling a simultaneous shift amount of multiple rows or columns of the two dimensional shift register array with each next iteration. The method also includes executing one or more instructions within respective lanes of the two dimensional execution lane array in between shifts of iterations. Another method is described that includes, on an image processor having a two dimensional execution lane array and a two dimensional shift register array, repeatedly executing one or more instructions within respective lanes of the execution lane array that select between content in different registers of a same array location in between repeated simultaneous shifts of multiple rows or columns of data in the two dimensional shift register array.

公开(公告)号：US11196953B2

公开(公告)日：2021-12-07

申请号：US16735050

申请日：2020-01-06

Applicant: Google LLC

Inventor： Albert Meixner ,  Daniel Frederic Finchelstein ,  David Patterson ,  William R. Mark ,  Jason Rupert Redgrave ,  Ofer Shacham

IPC: H04N5/225 ,  H04N5/374 ,  G06T1/20 ,  H04N5/341 ,  G06F5/01 ,  G06F12/02 ,  G06F17/16

Abstract: A method is described that includes, on an image processor having a two dimensional execution lane array and a two dimensional shift register array, repeatedly shifting first content of multiple rows or columns of the two dimensional shift register array and repeatedly executing at least one instruction between shifts that operates on the shifted first content and/or second content that is resident in respective locations of the two dimensional shift register array that the shifted first content has been shifted into.

公开(公告)号：US11190718B2

公开(公告)日：2021-11-30

申请号：US16859308

申请日：2020-04-27

Applicant: Google LLC

Inventor： Neeti Desai ,  Albert Meixner ,  Qiuling Zhu ,  Jason Rupert Redgrave ,  Ofer Shacham ,  Daniel Frederic Finchelstein

IPC: H04N5/369 ,  G06T1/60 ,  H04N5/91

Abstract: An apparatus is described that include a line buffer unit composed of a plurality of a line buffer interface units. Each line buffer interface unit is to handle one or more requests by a respective producer to store a respective line group in a memory and handle one or more requests by a respective consumer to fetch and provide the respective line group from memory. The line buffer unit has programmable storage space whose information establishes line group size so that different line group sizes for different image sizes are storable in memory.

公开(公告)号：US11138013B2

公开(公告)日：2021-10-05

申请号：US17001097

申请日：2020-08-24

Applicant: Google LLC

Inventor： Albert Meixner ,  Jason Rupert Redgrave ,  Ofer Shacham ,  Daniel Frederic Finchelstein ,  Qiuling Zhu

IPC: G06F9/38 ,  G06T1/20 ,  G06F9/30 ,  G06F15/80 ,  H04N3/14

Abstract: An apparatus that includes a program controller to fetch and issue instructions is described. The apparatus includes an execution lane having at least one execution unit to execute the instructions. The execution lane is part of an execution lane array that is coupled to a two dimensional shift register array structure, wherein, execution lane s of the execution lane array are located at respective array locations and are coupled to dedicated registers at same respective array locations in the two-dimensional shift register array.

公开(公告)号：US10754654B2

公开(公告)日：2020-08-25

申请号：US16368288

申请日：2019-03-28

Applicant: Google LLC

Inventor： Albert Meixner ,  Jason Rupert Redgrave ,  Ofer Shacham ,  Daniel Frederic Finchelstein ,  Qiuling Zhu

IPC: G06F9/38 ,  G06T1/20 ,  G06F9/30 ,  G06F15/80 ,  H04N3/14

Abstract: An apparatus that includes a program controller to fetch and issue instructions is described. The apparatus includes an execution lane having at least one execution unit to execute the instructions. The execution lane is part of an execution lane array that is coupled to a two dimensional shift register array structure, wherein, execution lane s of the execution lane array are located at respective array locations and are coupled to dedicated registers at same respective array locations in the two-dimensional shift register array.

公开(公告)号：US20200154072A1

公开(公告)日：2020-05-14

申请号：US16735050

申请日：2020-01-06

Applicant: Google LLC

Inventor： Albert Meixner ,  Daniel Frederic Finchelstein ,  David Patterson ,  William R. Mark ,  Jason Rupert Redgrave ,  Ofer Shacham

IPC: H04N5/374 ,  G06F17/16 ,  G06F12/02 ,  G06F5/01 ,  H04N5/341 ,  G06T1/20

Abstract: A method is described that includes, on an image processor having a two dimensional execution lane array and a two dimensional shift register array, repeatedly shifting first content of multiple rows or columns of the two dimensional shift register array and repeatedly executing at least one instruction between shifts that operates on the shifted first content and/or second content that is resident in respective locations of the two dimensional shift register array that the shifted first content has been shifted into.

公开(公告)号：US20200120287A1

公开(公告)日：2020-04-16

申请号：US16659702

申请日：2019-10-22

Applicant: Google LLC

Inventor： Qiuling Zhu ,  Ofer Shacham ,  Jason Rupert Redgrave ,  Daniel Frederic Finchelstein ,  Albert Meixner

IPC: H04N5/262 ,  G06T1/20 ,  G06T1/60

Abstract: In a general aspect, an apparatus can include image processing logic (IPL) configured to perform an image processing operation on pixel data corresponding with an image having a width of W pixels and a height of H pixels to produce output pixel data in vertical slices of K pixels using K vertically overlapping stencils of S×S pixels, K being greater than 1 and less than H, S being greater than or equal to 2, and W being greater than S. The apparatus can also include a linebuffer operationally coupled with the IPL, the linebuffer configured to buffer the pixel data for the IPL. The linebuffer can include a full-size buffer having a width of W and a height of (S−1). The linebuffer can also include a sliding buffer having a width of SB and a height of K, SB being greater than or equal to S and less than W.

公开(公告)号：US20200020069A1

公开(公告)日：2020-01-16

申请号：US16529633

申请日：2019-08-01

Applicant: Google LLC

Inventor： Albert Meixner ,  Hyunchul Park ,  William R. Mark ,  Daniel Frederic Finchelstein ,  Ofer Shacham

IPC: G06T1/20 ,  G06F8/41 ,  G06F9/50

Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for restructuring an image processing pipeline. The method includes compiling program code targeted for an image processor having programmable stencil processors composed of respective two-dimensional execution lane and shift register circuit structures. The program code is to implement a directed acyclic graph and is composed of multiple kernels that are to execute on respective ones of the stencil processors, wherein the compiling includes performing any of: horizontal fusion of kernels; vertical fusion of kernels; fission of one of the kernels into multiple kernels; spatial partitioning of a kernel into multiple spatially partitioned kernels; or splitting the directed acyclic graph into smaller graphs.

公开(公告)号：US20190220282A1

公开(公告)日：2019-07-18

申请号：US16368288

申请日：2019-03-28

Applicant: Google LLC

Inventor： Albert Meixner ,  Jason Rupert Redgrave ,  Ofer Shacham ,  Daniel Frederic Finchelstein ,  Qiuling Zhu

IPC: G06F9/38 ,  G06F9/30 ,  H04N3/14 ,  G06T1/20 ,  G06F15/80

Abstract: An apparatus that includes a program controller to fetch and issue instructions is described. The apparatus includes an execution lane having at least one execution unit to execute the instructions. The execution lane is part of an execution lane array that is coupled to a two dimensional shift register array structure, wherein, execution lane s of the execution lane array are located at respective array locations and are coupled to dedicated registers at same respective array locations in the two-dimensional shift register array.

公开(公告)号：US20180234653A1

公开(公告)日：2018-08-16

申请号：US15946095

申请日：2018-04-05

Applicant: Google LLC

Inventor： Albert Meixner ,  Daniel Frederic Finchelstein ,  David Patterson ,  William R. Mark ,  Jason Rupert Redgrave ,  Ofer Shacham

IPC: H04N5/374 ,  H04N5/341 ,  G06F5/01 ,  G06F17/16 ,  G06F12/02 ,  G06T1/20

CPC classification number: H04N5/3742 ,  G06F5/015 ,  G06F12/0207 ,  G06F17/16 ,  G06T1/20 ,  H04N5/341

Abstract: A method is described that includes, on an image processor having a two dimensional execution lane array and a two dimensional shift register array, repeatedly shifting first content of multiple rows or columns of the two dimensional shift register array and repeatedly executing at least one instruction between shifts that operates on the shifted first content and/or second content that is resident in respective locations of the two dimensional shift register array that the shifted first content has been shifted into.