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公开(公告)号:US11569205B2
公开(公告)日:2023-01-31
申请号:US17228393
申请日:2021-04-12
Applicant: Google LLC
Inventor: Theodore Charles White
IPC: H01L21/02 , H01L25/065 , G06N10/00 , H01L27/18 , H01L23/48 , H01L23/532 , H01L23/66 , H01L23/00 , H01L25/00 , H01P7/08
Abstract: A device includes: a first chip including a qubit; and a second chip bonded to the first chip, the second chip including a substrate including first and second opposing surfaces, the first surface facing the first chip, wherein the second chip includes a single layer of superconductor material on the first surface of the substrate, the single layer of superconductor material including a first circuit element. The second chip further includes a second layer on the second surface of the substrate, the second layer including a second circuit element. The second chip further includes a through connector that extends from the first surface of the substrate to the second surface of the substrate and electrically connects a portion of the single layer of superconducting material to the second circuit element.
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公开(公告)号:US20220311400A1
公开(公告)日:2022-09-29
申请号:US17632923
申请日:2020-08-03
Applicant: Google LLC
Inventor: Theodore Charles White , Anthony Edward Megrant
Abstract: A parametric traveling wave amplifier (200) is disclosed in which the amplifiers include: a co-planar waveguide, in which the co-planar waveguide includes at least one Josephson junction (210) interrupting a center trace (204) of the co-planar waveguide; and at least one shunt capacitor coupled to the co-planar waveguide, in which each shunt capacitor of the at least one shunt capacitor includes a corresponding superconductor trace (214) extending over an upper surface of the center trace of the co-planar waveguide, and in which a gap separates the superconductor trace from the upper surface of the center trace, and in which the co-planar waveguide including the at least one Josephson junction and the shunt capacitor establish a predefined overall impedance for the traveling wave parametric amplifier.
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公开(公告)号:US11411159B1
公开(公告)日:2022-08-09
申请号:US17104826
申请日:2020-11-25
Applicant: Google LLC
Inventor: Theodore Charles White , John Martinis
IPC: H05K1/02 , H01L39/02 , H01L39/04 , H03F19/00 , H01P1/383 , H01L39/22 , G06N10/00 , H01P5/18 , B82Y10/00
Abstract: An integrated qubit readout circuit is presented, which includes a superconducting parametric amplifier, a circuit board arranged to mount the superconducting parametric amplifier, a circulator mounted on the circuit board and connected to the superconducting parametric amplifier, wherein the circulator comprises a termination port electrically connected to a termination resistor arranged to terminate a pump tone received by the superconducting parametric amplifier, and wherein the termination resistor is mounted on the circuit board.
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公开(公告)号:US20210336121A1
公开(公告)日:2021-10-28
申请号:US16964053
申请日:2019-07-25
Applicant: Google LLC
Inventor: Brian James Burkett , Ofer Naaman , Anthony Edward Megrant , Theodore Charles White
Abstract: Methods, systems and apparatus for forming Josephson junctions with reduced stray inductance. In one aspect, a device includes a substrate; a first superconductor layer on the substrate; an insulator layer on the first superconductor layer; a second superconductor layer on the insulator layer, wherein the first superconductor layer, the insulator layer, and the second superconductor layer form a superconductor tunnel junction; and a third superconductor layer directly on a surface of the first superconductor layer and directly on a surface of the second superconductor layer to provide a first contact to the superconducting tunnel junction and a second contact to the superconductor tunnel junction, respectively.
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