Inter-port communication in a multi-port memory device
    21.
    发明授权
    Inter-port communication in a multi-port memory device 有权
    多端口存储设备中的端口间通信

    公开(公告)号:US07949863B2

    公开(公告)日:2011-05-24

    申请号:US11694819

    申请日:2007-03-30

    IPC分类号: G06F9/48 G06F15/76

    摘要: A method and system for inter-port communication utilizing a multi-port memory device. The memory device contains an interrupt register, an interrupt signal interface (e.g., a dedicated pin), an interrupt mask, and one or more message buffers associated with each port. When a first component coupled to a first port of the memory device wants to communicate with a second component coupled to a second port of the memory device, the first component writes a message to a message buffer associated with the second port. An interrupt in the input register of the second port is set to notify the second component coupled to the second port that a new message is available. Upon receiving the interrupt, the second component reads the interrupt register to determine the nature of the interrupt. The second component then reads the message from the message buffer.

    摘要翻译: 一种利用多端口存储器件进行端口间通信的方法和系统。 存储器件包含中断寄存器,中断信号接口(例如,专用引脚),中断掩码以及与每个端口相关联的一个或多个消息缓冲器。 当耦合到存储设备的第一端口的第一组件想要与耦合到存储器设备的第二端口的第二组件通信时,第一组件将消息写入与第二端口相关联的消息缓冲器。 第二端口的输入寄存器中的中断被设置为通知耦合到第二端口的第二组件新消息可用。 在接收到中断时,第二个组件读取中断寄存器以确定中断的性质。 然后第二个组件从消息缓冲区读取消息。

    Coding system for memory systems employing high-speed serial links
    22.
    发明授权
    Coding system for memory systems employing high-speed serial links 有权
    使用高速串行链路的存储器系统的编码系统

    公开(公告)号:US07777652B2

    公开(公告)日:2010-08-17

    申请号:US12260972

    申请日:2008-10-29

    IPC分类号: H03M7/00

    CPC分类号: H03M5/145

    摘要: A method, apparatus and system employing a coder is disclosed. The coder to receive an incoming stream including a first code block and a second code block, and partition the first code block into first small code blocks, and partition the second code block into second small code blocks. The coder is further to code a memory that uses one or more serial lines for communication is performed, wherein coding includes coding the first small code blocks of the first code block and the second small code blocks of the second code block, wherein the coding of the first and second blocks is performed such that a maximum run length is maintained.

    摘要翻译: 公开了一种采用编码器的方法,装置和系统。 编码器,用于接收包括第一代码块和第二代码块的输入流,并将第一代码块划分为第一小代码块,并将第二代码块划分成第二小代码块。 编码器进一步编码使用一个或多个串行线进行通信的存储器,其中编码包括对第一代码块的第一小代码块和第二代码块的第二小代码块进行编码,其中编码 执行第一和第二块,使得保持最大行程长度。

    Transmission of alternative content over standard device connectors
    24.
    发明授权
    Transmission of alternative content over standard device connectors 有权
    通过标准设备连接器传输替代内容

    公开(公告)号:US08176214B2

    公开(公告)日:2012-05-08

    申请号:US12606096

    申请日:2009-10-26

    IPC分类号: G06F13/10

    摘要: Transmission of alternative content over standard device connectors. An embodiment of a method includes connecting a first device to a second device utilizing a standard connector, the connector including multiple pins, and detecting whether the second device is operating in a standard mode or an alternative mode. If the second device is operating in the alternative mode, then switching one or more pins of the standard connector for the alternative mode and transmitting or receiving signals for the alternative mode via the plurality of pins of the standard connector.

    摘要翻译: 通过标准设备连接器传输替代内容。 一种方法的实施例包括使用标准连接器将第一设备连接到第二设备,连接器包括多个引脚,以及检测第二设备是否以标准模式或替代模式操作。 如果第二设备在替代模式下操作,则切换用于替代模式的标准连接器的一个或多个引脚,以及通过标准连接器的多个引脚发送或接收替代模式的信号。

    Method, apparatus, and system for automatic data aligner for multiple serial receivers
    25.
    发明授权
    Method, apparatus, and system for automatic data aligner for multiple serial receivers 有权
    用于多个串行接收器的自动数据对准器的方法,装置和系统

    公开(公告)号:US08036248B2

    公开(公告)日:2011-10-11

    申请号:US12260970

    申请日:2008-10-29

    IPC分类号: H04J3/06

    摘要: A method, apparatus and system for employing an automatic data aligner for multiple serial receivers in serial link technologies is provided. In one embodiment, converting a transmission data path of a single bit into a parallel bit via a data aligner, wherein the data is being transmitted via one or more ports. Further, binding data transmission channels to reduce latency in transmission of the data, wherein the binding of the data transmission channels further includes inserting delay to match latency via the one or more ports.

    摘要翻译: 提供了一种在串行链路技术中采用多个串行接收机的自动数据对准器的方法,装置和系统。 在一个实施例中,经由数据对准器将单个位的传输数据路径转换为并行位,其中数据正通过一个或多个端口传输。 此外,绑定数据传输信道以减少数据传输中的等待时间,其中数据传输信道的绑定还包括插入延迟以经由一个或多个端口匹配等待时间。

    17B/20B coding system
    26.
    发明授权
    17B/20B coding system 有权
    17B / 20B编码系统

    公开(公告)号:US07978099B2

    公开(公告)日:2011-07-12

    申请号:US12847416

    申请日:2010-07-30

    IPC分类号: H03M7/00

    CPC分类号: H03M5/145

    摘要: A method, apparatus and system employing a 17B/20B coder is disclosed. The 17B/20B coder to receive an incoming stream including a 17B block and a 20B block, and partition the 17B block into first blocks, and partitioning the 20B into second blocks. The coder is further to code 17B to 20B of memory using one or more serial lines for communication is performed, wherein coding includes coding the first blocks of the 17B block and the second blocks of the 20B block, wherein the coding of the first and second blocks is performed such that a maximum run length is maintained.

    摘要翻译: 公开了一种采用17B / 20B编码器的方法,装置和系统。 17B / 20B编码器,用于接收包括17B块和20B块的进入流,并将17B块分割成第一块,并将20B划分成第二块。 编码器还使用一条或多条用于通信的串行线对存储器的17B至20B进行编码,其中编码包括对17B块的第一块和20B块的第二块进行编码,其中第一和第二 执行块,使得保持最大游程长度。