公开(公告)号：US20240201774A1

公开(公告)日：2024-06-20

申请号：US18589263

申请日：2024-02-27

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Hyun Ju Yi ,  Jaeho Sim ,  Kicheol Eom ,  Dong-Ryoul Lee ,  Hyotaek Leem

IPC分类号： G06F1/3234 ,  G06F13/16 ,  G06F13/42 ,  G11C5/14 ,  G11C16/30 ,  G11C16/32

CPC分类号： G06F1/3275 ,  G06F13/1689 ,  G06F13/4243 ,  G06F13/4273 ,  G11C5/14 ,  G11C16/30 ,  G11C16/32

摘要： A storage controller communicates with an external device including a submission queue and a completion queue. An operation method of the storage controller includes receiving a notification associated with a command from the external device, based on a first clock, fetching the command from the submission queue, based on a second clock, performing an operation corresponding to the fetched command, based on a third clock, writing completion information to the completion queue, based on a fourth clock, and transmitting an interrupt signal to the external device, based on a fifth clock. Each of the first clock to the fifth clock is selectively activated depending on each operation phase.

公开(公告)号：US11868302B2

公开(公告)日：2024-01-09

申请号：US17955086

申请日：2022-09-28

申请人： WAGO VERWALTUNGSGESELLSCHAFT MBH

发明人： Daniel Jerolm ,  Hans-Herbert Kirste ,  Frank Schadde ,  Gerald Huse

IPC分类号： G06F13/42 ,  G06F13/374 ,  H04L12/40 ,  H04L12/42

CPC分类号： G06F13/4243 ,  G06F13/374 ,  H04L12/40019 ,  H04L12/40032 ,  H04L12/42

摘要： A data bus subscriber connected to a local bus, particularly a ring bus. The data bus subscriber has a status signal input for receiving a first status signal value from a downstream data bus subscriber or a terminator, a status signal output for providing a second status signal value to an upstream data bus subscriber or to a local bus master, wherein the data bus subscriber is adapted to provide the second status signal value based on a logical link of a communication readiness of the data bus subscriber and the first status signal value. The invention further relates to a corresponding method and a local bus.

公开(公告)号：US11749336B2

公开(公告)日：2023-09-05

申请号：US17521379

申请日：2021-11-08

申请人： Rambus Inc.

发明人： Jared L. Zerbe ,  Frederick A. Ware

IPC分类号： G06F1/04 ,  G11C11/4076 ,  G06F13/42 ,  G11C7/10 ,  G11C7/22 ,  G11C7/04 ,  G11C29/02 ,  H04L7/00

CPC分类号： G11C11/4076 ,  G06F1/04 ,  G06F13/4243 ,  G11C7/1093 ,  G11C7/22 ,  G11C7/222 ,  G11C7/04 ,  G11C7/1078 ,  G11C29/022 ,  G11C29/023 ,  G11C29/028 ,  G11C2207/2254 ,  H04L7/0008 ,  Y02D10/00

摘要： A method of operating a memory controller is disclosed. The method includes transmitting data signals to a memory device over each one of at least two parallel data links. A timing signal is sent to the memory device on a first dedicated link. The timing signal has a fixed phase relationship with the data signals. A data strobe signal is driven to the memory device on a second dedicated link. Phase information is received from the memory device. The phase information being generated internal to the memory device and based on a comparison between the timing signal and a version of the data strobe signal internally distributed within the memory device. A phase of the data strobe signal is adjusted relative to the timing signal based on the received phase information.

公开(公告)号：US11664067B2

公开(公告)日：2023-05-30

申请号：US17391521

申请日：2021-08-02

申请人： Rambus Inc.

发明人： Frederick A. Ware

IPC分类号： G06F13/16 ,  G06F13/42 ,  G11C7/10 ,  G11C11/409 ,  G11C11/4076 ,  G11C7/22 ,  G11C8/18 ,  G06F1/10

CPC分类号： G11C11/4076 ,  G06F1/10 ,  G06F13/1689 ,  G06F13/4243 ,  G11C7/1072 ,  G11C7/22 ,  G11C8/18 ,  G11C11/409 ,  G11C2207/2254

摘要： An integrated circuit device outputs a sequence of differently delayed calibration data timing signals to a DRAM component via a data-signal timing line as part of a timing calibration operation and then stores a delay value, based on at least one of the calibration data timing signals, that compensates for a difference in signal propagation times over the data-signal timing line and a command/address-signal timing line. After the timing calibration operation, the integrated circuit device outputs write data to the DRAM component and outputs a write data timing signal, delayed according to the delay value, to via the data-signal timing line to time reception of the first write data within the DRAM.

公开(公告)号：US20180336942A1

公开(公告)日：2018-11-22

申请号：US16049693

申请日：2018-07-30

申请人： Uniquify IP Company, LLC

发明人： Mahesh Gopalan ,  David Wu ,  Venkat Iyer

IPC分类号： G11C11/4076 ,  G11C11/4093 ,  G11C7/22 ,  G11C7/10 ,  G06F13/42 ,  G06F1/08 ,  G06F12/06 ,  G06F3/06 ,  G06F1/14 ,  G06F1/12 ,  G06F13/16

CPC分类号： G11C11/4076 ,  G06F1/04 ,  G06F1/08 ,  G06F1/12 ,  G06F1/14 ,  G06F3/0619 ,  G06F3/065 ,  G06F3/067 ,  G06F12/0646 ,  G06F13/1689 ,  G06F13/4243 ,  G11C7/04 ,  G11C7/1072 ,  G11C7/222 ,  G11C11/40 ,  G11C11/4093 ,  G11C11/4096 ,  G11C29/022 ,  G11C29/023 ,  G11C29/028

摘要： In accordance with one embodiment, an apparatus is provided, comprising: a double data rate (DDR) memory controller that, when in operation, causes the apparatus to: capture a data bit input signal in a first core domain register that is communicatively coupled to a second core domain register; clock the first core domain register utilizing a first clock; clock the second core domain register utilizing a second clock; maintain a difference in time between an active edge of the second clock and a next active edge of the first clock, such that the difference in time corresponds to a capture clock delay value; and set the capture clock delay value during a power-on initialization calibration operation.

公开(公告)号：US10079047B2

公开(公告)日：2018-09-18

申请号：US15389795

申请日：2016-12-23

申请人： VIA TECHNOLOGIES, INC.

发明人： Vanessa Canac ,  James R. Lundberg

IPC分类号： G06F1/12 ,  G11C7/10 ,  G06F13/42 ,  G11C8/18 ,  G06F13/362 ,  G06F13/40

CPC分类号： G11C7/1072 ,  G06F1/12 ,  G06F13/3625 ,  G06F13/4068 ,  G06F13/4217 ,  G06F13/4243 ,  G11C8/18

摘要： A method is provided that compensates for misalignment on a synchronous data bus. The method includes: replicating propagation path lengths, loads, and buffering of a radial distribution network for a strobe; receiving a first signal, and generating a second signal by employing the replicated propagation path lengths, loads, and buffering; when an update signal is asserted, when an update signal is asserted, measuring a propagation time beginning with assertion of the first signal and ending with assertion of the second signal by selecting one of a plurality of successively delayed versions of the first signal that coincides with the assertion of the second signal, wherein said selecting comprises incrementing and decrementing bus states of select inputs on a mux, wherein the plurality of successively delayed versions of the first signal comprises inputs to the mux; gray encoding a value on a lag bus that indicates the propagation time; and receiving one of a plurality of radially distributed strobes and a data bit, and delaying registering of the data bit by the propagation time. The receiving includes generating successively delayed versions of the data bit; receiving the value on the lag bus, and selecting one of the successively delayed versions of the data bit that corresponds to the value; and registering the state of the one of the successively delayed versions of the data bit upon assertion of one of a plurality of radially distributed strobe signals.

公开(公告)号：US10014042B2

公开(公告)日：2018-07-03

申请号：US15481798

申请日：2017-04-07

申请人： SK hynix Inc.

发明人： Yun Gi Hong

IPC分类号： G11C7/22 ,  H04L7/00 ,  G11C7/10 ,  G06F13/42 ,  H03L7/081 ,  H04L7/033

CPC分类号： G11C7/222 ,  G06F13/4243 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/1093 ,  H03L7/0814 ,  H04L7/0037 ,  H04L7/0045 ,  H04L7/033

摘要： A semiconductor device includes an input/output control circuit configured to generate a first driving signal and a second driving signal by shifting a latency signal in synchronization with a clock, and generating a strobe signal which toggles according to logic levels of the first driving signal and the second driving signal; and a data input/output circuit configured to latch input data in synchronization with the strobe signal, and outputting the latched input data as output data.

公开(公告)号：US20180173650A1

公开(公告)日：2018-06-21

申请号：US15666739

申请日：2017-08-02

申请人： SK hynix Inc.

发明人： Chan-Jong WOO

IPC分类号： G06F13/16 ,  G11C8/18 ,  G06F13/42

CPC分类号： G06F13/1636 ,  G06F13/4243 ,  G11C5/04 ,  G11C7/222 ,  G11C8/18

摘要： A method for operating a memory system including a memory controller and a memory mudule, the method includes: by the memory controller, applying a read command to the memory module; by the memory module, determining whether the memory module is able to transfer the read data to the memory controller during a regulated section; by the memory module, notifying the memory controller by using a data strobe signal that the memory module is not able to transfer the read data to the memory controller during the regulated section; by the memory controller, applying a status check-out command to the memory module in response to the notification for checking out a status of the memory module; and by the memory module, transferring status information of the memory module to the memory controller in response to the status check-out command.

公开(公告)号：US20180137066A1

公开(公告)日：2018-05-17

申请号：US15353189

申请日：2016-11-16

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Martin A. ROSS

IPC分类号： G06F13/16 ,  G06F13/42

CPC分类号： G06F13/1642 ,  G06F13/161 ,  G06F13/4239 ,  G06F13/4243

摘要： A method receives an inbound request to be processed based on multiple outbound service invocations of multiple outbound services. The method accesses expected response times for the inbound request for each of the multiple outbound services. The method determines which one or more of the multiple outbound services to invoke asynchronously and which one or more of the multiple outbound services to invoke synchronously based on the expected response times for the inbound request for each of the multiple outbound services. The method invokes asynchronously the one or more of the multiple outbound services determined to be invoked asynchronously, invokes synchronously the one or more of the multiple outbound services determined to be invoked synchronously.

公开(公告)号：US20180129427A1

公开(公告)日：2018-05-10

申请号：US15807720

申请日：2017-11-09

申请人： Conversant Intellectual Property Management Inc.

发明人： Jin-Ki KIM ,  Hong Beom PYEON

IPC分类号： G06F3/06 ,  G11C16/34 ,  G06F13/42 ,  G11C7/10 ,  G11C8/10 ,  G11C16/06 ,  G11C16/10 ,  G11C16/26 ,  G11C16/08 ,  G11C16/16 ,  G11C5/06

CPC分类号： G06F3/0611 ,  G06F3/0655 ,  G06F3/0688 ,  G06F13/4243 ,  G11C5/066 ,  G11C7/1021 ,  G11C7/1051 ,  G11C7/1078 ,  G11C8/10 ,  G11C16/06 ,  G11C16/08 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  G11C16/3459 ,  G11C2207/107 ,  G11C2216/30

摘要： An apparatus, system, and computer-implemented method for controlling data transfer between a plurality of serial data link interfaces and a plurality of memory banks in a semiconductor memory is disclosed. In one example, a flash memory device with multiple links and memory banks, where the links are independent of the banks, is disclosed. The flash memory devices may be cascaded in a daisy-chain configuration using echo signal lines to serially communicate between memory devices. In addition, a virtual multiple link configuration is described wherein a single link is used to emulate multiple links.