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    COMPUTE EXPRESS LINK (CXL) DRAM BLADE MEMORY
    2.
    发明公开
    COMPUTE EXPRESS LINK (CXL) DRAM BLADE MEMORY 审中-公开

    公开(公告)号：US20240281275A1

    公开(公告)日：2024-08-22

    申请号：US18433181

    申请日：2024-02-05

    Applicant: Micron Technology, Inc.

    Inventor： Satheesh Babu MUTHUPANDI

    IPC: G06F9/455 ,  G06F13/40

    CPC classification number: G06F9/45558 ,  G06F13/4022 ,  G06F13/409 ,  G06F2009/45583

    Abstract: A system comprises a chassis; a Compute Express Link (CXL) back plane interface mounted within the chassis; a first printed circuit board housed within the chassis and connected to the CXL back plane interface, the first printed circuit board including processing circuitry, switching circuitry and a memory; and a blade server comprising a second printed circuit board housed within the chassis and connected to the CXL back plane interface. The processing circuitry is configured to control the switching circuitry to allocate at least a portion of the memory to the blade server such that a virtual machine provided by the blade server can access the allocated memory through the CXL back plane interface in addition to its own dedicated memory provided by the blade server.

    Method for reading information from riser cards and baseboard management control module implementing the same
    3.
    发明授权
    Method for reading information from riser cards and baseboard management control module implementing the same 有权

    公开(公告)号：US12061565B2

    公开(公告)日：2024-08-13

    申请号：US18184506

    申请日：2023-03-15

    Applicant: Mitac Computing Technology Corporation

    Inventor： Chih-Wei Lee

    IPC: G06F13/40 ,  G06F1/18

    CPC classification number: G06F13/409 ,  G06F1/185

    Abstract: A method for reading information from multiple riser cards is implemented by a BMC module that includes an SMBus controller, where the riser cards are electrically connected to the SMBus controller. The method includes steps of: accessing a lookup table and a plurality of bus addresses; scanning a target address for communicating with a target card; determining whether a slave address has been received from the target card; when the BMC module determines that the slave address has been received from the target card, reading a memory of the target card according to a target reading spec to obtain identification information; determining whether the identification information conforms to an FRU header format; and when the BMC module determines that the identification information conforms to the FRU header format, reading the memory of the target card to obtain FRU information.

    AUTOMATIC PROVISION OF HIGH SPEED SERIALIZER/DESERIALIZER LANES BY FIRMWARE
    5.
    发明公开
    AUTOMATIC PROVISION OF HIGH SPEED SERIALIZER/DESERIALIZER LANES BY FIRMWARE 审中-公开

    公开(公告)号：US20240004822A1

    公开(公告)日：2024-01-04

    申请号：US17854490

    申请日：2022-06-30

    Applicant: Advanced Micro Devices, Inc.

    Inventor： George D. Azevedo ,  Peter Malcolm Barnes ,  Michael J. Tresidder

    IPC: G06F13/40 ,  G06F13/42 ,  G06F15/78

    CPC classification number: G06F13/409 ,  G06F13/4221 ,  G06F15/7807

    Abstract: Systems, apparatuses, and methods for automatic firmware provision of high speed serializer/deserializer (SERDES) links are disclosed. A system on chip (SoC) includes one or more microcontrollers, a programmable interconnect, a plurality of physical layer engines, and a plurality of SERDES lanes. The programmable interconnect and the plurality of SERDES lanes are able to support communication protocols for interfaces such as PCIE, SATA, Ethernet, and others. On bootup, the SoC receives a custom specification of how the plurality of SERDES lanes are to be configured. The one or more microcontrollers generate a mapping for the programmable interconnect based on the specification. The mapping is used to configure the programmable interconnect to match the specification. The result is the programmable interconnect connecting the plurality of SERDES lanes to the appropriate physical layer circuits to implement the desired configuration.

    Edge computing device with connector pin authentication for peripheral device
    7.
    发明授权
    Edge computing device with connector pin authentication for peripheral device 有权

    公开(公告)号：US11829465B2

    公开(公告)日：2023-11-28

    申请号：US17077982

    申请日：2020-10-22

    Applicant: MORPHIX, INC.

    Inventor： Jonathan Lovegrove

    IPC: G06F21/00 ,  H04L29/06 ,  G06F21/44 ,  G06F21/85 ,  G06F13/40 ,  H04L9/40 ,  G06F21/60

    CPC classification number: G06F21/44 ,  G06F13/409 ,  G06F13/4068 ,  G06F21/602 ,  G06F21/85 ,  H04L63/0853

    Abstract: A computing device is provided that includes a processor having a plurality of pins that are electrically coupled to a plurality of pins of a connector, and a memory device storing a state table that maps the plurality of pins of the connector to a plurality of connection types. The processor is configured to perform an authentication process for at least one connection type to determine whether an authenticated device configured for the at least one connection type is coupled to the connector. The authentication process is performed at least in part by sending an authentication signal to one or more of the plurality of pins of the connector mapped to the at least one connection type, and receiving an expected authentication signal response on one or more of the plurality of pins of the connector mapped to the at least one connection type.

    UART aggregation and JTAG selection circuitry for a multi-solid state drive environment
    10.
    发明授权
    UART aggregation and JTAG selection circuitry for a multi-solid state drive environment 有权

    公开(公告)号：US11809355B2

    公开(公告)日：2023-11-07

    申请号：US17169062

    申请日：2021-02-05

    Applicant: SK hynix Inc.

    Inventor： Lock Duc Nguyen ,  Akshay Ganesh ,  Priyadarsini Lanka ,  Ping Zheng ,  Xiaofang Chen

    IPC: G06F13/38 ,  H03K19/173 ,  G06F13/40

    CPC classification number: G06F13/385 ,  G06F13/387 ,  G06F13/409 ,  H03K19/1737

    Abstract: An adaptor device includes a first interface for coupling to a first processor, a second interface for coupling to a second processor, the second interface being different than the first interface, and a plurality of third interfaces, which are different than either the first interface or the second interface. The plurality of third interfaces are configured for coupling to a corresponding plurality of external devices. The adaptor device is configured to receive, at the first interface, a first signal from the first processor. In response to the first signal, the adaptor device couples through the plurality of third interfaces to the plurality of external devices to enable the first processor substantially concurrent access to the plurality of external devices. The adaptor device is also configured to receive, at the first interface, a second signal from the first processor. In response to the second signal, the adaptor device couples the second processor with a selected one of the plurality of external devices.

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