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公开(公告)号:US20210001635A1
公开(公告)日:2021-01-07
申请号:US16977675
申请日:2018-12-03
Applicant: Hewlett-Packard Development Company, L.P.
Inventor: James Michael GARDNER , Scott A. LINN , Stephen D. PANSHIN , Jefferson P. WARD , David Owen ROETHIG
Abstract: In an example, a logic circuit comprising a communications interface including a data contact to communicate via a communications bus, an enablement contact, separate from the communication interface, to receive an input to enable the logic circuit, and at least one memory register, comprising at least one reconfigurable address register. The logic circuit may be configured, such that, when enabled, it responds to communications sent via the communication bus which are addressed to the address held in a reconfigurable address register.
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公开(公告)号:US20200174963A1
公开(公告)日:2020-06-04
申请号:US16781052
申请日:2020-02-04
Applicant: Hewlett-Packard Development Company, L.P.
Inventor: Stephen D. PANSHIN , Scott A. LINN
Abstract: Logic circuitry packages for association with replaceable print apparatus components are disclosed herein. An example logic circuitry package includes a timer and a serial data bus interface including a data contact and a clock contact, the serial data bus interface to interface with a serial data bus of a printer. The example logic circuitry package also includes logic circuitry to, in response to a first command sent to the logic circuitry package via the serial data bus of the printer: initiate a low voltage on the data contact; wait for a time period tracked by the timer to expire, without reference to a clock signal at the clock contact from the serial data bus; and upon expiration of the time period, cause the data contact to assume a second voltage different than the low voltage. The first command specifies a duration of the time period and the example logic circuitry is to maintain the low voltage on the data contact based on the duration of the time period.
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