摘要:
Offset canceling amplifier circuit in which a high accuracy of output with a suppressed output offset is achieved and a variation in a slew rate is also suppressed, and a display device having the amplifier circuit. A first differential pair (M5, M6) connected between a first current source (M9) and a common load circuit (M1, M2) and a second differential pair (M3, M4) connected between a second current source (M8) between the common load circuit (M1, M2) are provided. A switch (SW1) connected between one input of the first differential pair (M5, M6) and an input terminal (1), a switch (SW2) connected between the one input of the differential pair (M5, M6) and an output terminal (2), a switch (SW3) connected between one input of the second differential pair (M3, M4) and the output terminal (2), and a capacitance element (C1) connected to the one input of the second differential pair (M3, M4) are provided. The other input of the first differential pair (M5, M6) is connected to the input terminal (1), and the other input of the second differential pair (M3, M4) is connected to a reference voltage input terminal (3). An amplifying operation by an amplifying element (M7) is performed responsive to a common output signal of the two differential pairs, and circuits (SW11, SW12) for controlling activation or deactivation of at least one of the first and second current sources are provided.
摘要:
A differential amplifier has first and second input terminals (T1, T2), an output terminal, a differential stage connected to the first and second input terminals, and an amplification stage having an input terminal thereof connected to an output terminal of the differential stage and an output terminal thereof connected to the output terminal. The differential stage includes a first differential pair with one of an input pair thereof connected to the first input terminal (T1) and the other connected to the output terminal, a second differential pair with one of an input pair thereof connected to the first input terminal (T1) and the other connected to the second input terminal (T2), a first current source for supplying current to the first differential pair, a second current source for supplying current to the second differential pair, and a load circuit connected to the output pairs of the first and second differential pairs. One of the output pair of the first differential pair is connected in common to one of the output pair of the second differential pair, and their common connection node constitutes the output terminal of the differential stage.
摘要:
There is provided a decoder in which a matrix of transistors, a plurality of reference voltage signal lines arranged on a first interconnect layer and extended in a row direction, being separated to one another over the matrix, and a plurality of reference voltage signal lines arranged on a second interconnect layer and extended in the row direction, being separated to one another over the matrix. The reference voltage signal lines on the mutually different layers are respectively connected to impurity diffusion layers of the transistors that are adjacent in the row direction. The reference voltage signal lines on the mutually different layers are respectively connected to the impurity diffusion layers of the transistors that are adjacent in a column direction.
摘要:
A display panel driver includes a color reducing circuit and a driving section. The driving section is configured to drive a first pixel and a second pixel. If a second input image data and a third input image data corresponding to the second pixel are supplied as an image data of a second image display format, then the color reducing circuit generates a third color reduction image data and a fourth color reduction image data. If the first input image data is supplied as the image data of the first image display format, then the first selector selects the third error value, and if the second input image data and the third input image data are supplied as the image data of the second image display format, then the first selector selects the second error value.
摘要:
A decoder includes a first sub-decoder that receives a first level voltage set and outputs voltages selected according to lower L-bits of N-bit data, a second sub-decoder that receives a second level voltage set and outputs voltages selected according to the lower L-bits, a third sub-decoder that selects, according to higher M-bits, one voltage from the voltages selected by the first and second sub-decoders, a fourth sub-decoder that outputs voltages selected according to lower P-bits from among a third level voltage set, a fifth sub-decoder that selects one voltage selected according to higher Q-bits from the voltages output from the fourth sub-decoder, and a sixth sub-decoder that controls conduction and non-conduction based on K-bits, between one output among outputs of the first sub-decoder, and one output among outputs of the fourth sub-decoder; output of the third sub-decoder and output of the fifth sub-decoder are connected to an output terminal; the first, second, and third sub-decoders are configured from transistor switches of said first polarity, and the fourth, fifth, and sixth sub-decoders are configured from transistor switches of said second polarity.
摘要:
A differential amplifier has first and second input terminals (T1, T2), an output terminal, a differential stage connected to the first and second input terminals, and an amplification stage having an input terminal thereof connected to an output terminal of the differential stage and an output terminal thereof connected to the output terminal. The differential stage includes a first differential pair with one of an input pair thereof connected to the first input terminal (T1) and the other connected to the output terminal, a second differential pair with one of an input pair thereof connected to the first input terminal (T1) and the other connected to the second input terminal (T2), a first current source for supplying current to the first differential pair, a second current source for supplying current to the second differential pair, and a load circuit connected to the output pairs of the first and second differential pairs. One of the output pair of the first differential pair is connected in common to one of the output pair of the second differential pair, and their common connection node constitutes the output terminal of the differential stage.
摘要:
An output circuit includes a connection switch and an operation unit. The connection switch receives first and second voltages from first and second terminals, respectively, selects and outputs the first voltage or the second voltage for first to third intermediate terminals, including selection of the same voltage and switches assignment of the first and second voltages to the first to third intermediate terminals responsive to a connection switching signal. The operation unit receives the voltages assigned to the first to third intermediate terminals and outputs to an output terminal a voltage obtained by performing a predetermined operation on the voltages.
摘要:
An output circuit includes a connection switch and an operation unit. The connection switch includes first to third terminals for receiving first to third voltages, respectively, selects and outputs the first voltage or the second voltage or the third voltage to each of the first to seventh intermediate terminals, including selection of the same voltage for a plurality of the intermediate terminals. The connection switch switches assignment of the first to third voltages to the first to seventh intermediate terminals responsive to a connection switching signal. The operation unit receives the voltages assigned to the first to seventh intermediate terminals and outputs to an output terminal a voltage obtained by performing a predetermined operation on the voltages supplied to the first to seventh intermediate terminals.
摘要:
Disclosed is a level shift circuit including a first level shift circuit that is connected between a first power supply terminal and first and second output terminals and receives first and second input signals from the first and second input terminals, respectively, and sets one of the first and second output terminals to a first voltage level, based on the first and second input signals; a second level shift circuit that is connected between a second power supply terminal and the first and second output terminals, and sets the other of the first and second terminals to a second voltage level; and a circuit that performs control to disconnect a current path in the second level shifter between the second power supply terminal and one of the first and second output terminals that is driven to the second voltage level at a time point when the first and second input signals are supplied to the first and second input terminals for a predetermined period including the time point when the first and second input signals are supplied to the first and second input terminals, and to cancel the disconnection of the current path in the second level shifter between the one output terminal and the second power supply terminal after the predetermined period. Output amplitudes at the first and second output terminals are set to be larger than amplitudes of the first and second input signals.
摘要:
Disclosed is an output circuit including a connection switch and an operation unit. The connection switch receives first and second voltages from first and second terminals, respectively, selects and outputs the first voltage or the second voltage for first to third intermediate terminals, including selection of the same voltage and switches assignment of the first and second voltages to the first to third intermediate terminals responsive to a connection switching signal. The operation unit receives the voltages assigned to the first to third intermediate terminals and outputs to an output terminal a voltage obtained by performing a predetermined operation on the voltages.