公开(公告)号：US20090109572A1

公开(公告)日：2009-04-30

申请号：US12209868

申请日：2008-09-12

申请人： Toru Watanabe

发明人： Toru Watanabe

IPC分类号： G11B5/60

CPC分类号： G11B5/6082 ,  G11B5/6064

摘要： A head slider includes a leading end and a trailing end, a main top face and two step faces. The main top face faces a recording medium and forms a part of the leading end. The two step faces extend from the leading end to a downstream side at a lower position than the main top face when the main top face is placed face up. The step faces are respectively provided at the right and left sides with respect to the airflow. The main top face extends between the two step faces. The other portion of the main top face extends at the rear side of the step faces. At least a part of the head slider floats above the recording medium.

摘要翻译： 头部滑块包括前端和后端，主顶面和两个台阶面。 主顶面面向记录介质，形成前端的一部分。 当主顶面朝上放置时，两个台阶面从主顶面向下游侧延伸到比主顶面更低的位置。 阶梯面相对于气流分别设置在左右两侧。 主顶面在两个步骤面之间延伸。 主顶面的另一部分在台阶面的后侧延伸。 头部滑块的至少一部分浮动在记录介质上方。

公开(公告)号：US20050024162A1

公开(公告)日：2005-02-03

申请号：US10881752

申请日：2004-06-30

申请人： Toru Watanabe ,  Yutaka Takada ,  Makoto Inoguchi ,  Aritsugu Yajima ,  Kazuaki Tanaka ,  Shigekazu Takagi

发明人： Toru Watanabe ,  Yutaka Takada ,  Makoto Inoguchi ,  Aritsugu Yajima ,  Kazuaki Tanaka ,  Shigekazu Takagi

IPC分类号： H04B1/3822 ,  H04B1/40 ,  H01P1/213

CPC分类号： H04B1/006 ,  H04B1/0057 ,  H04B1/406 ,  H04B1/52

摘要： A high-frequency composite component is provided by placing an antenna on a multi-layer wiring board, placing a multiplexer/demultiplexer circuit, first and second matching circuits, and first and second balanced-to-unbalanced transformer circuits inside the board respectively, and providing first to fourth input and output terminals on the side surface of the board. The antenna is connected to the multiplexer/demultiplexer circuit via a first unbalanced line path, and the multiplexer/demultiplexer is connected to the first and second matching circuits via second and third unbalanced line paths, respectively. The first and second matching circuits are connected to the first and second balanced-to-unbalanced transformer circuits, respectively, via fourth and fifth unbalanced line paths, respectively. The respective balanced terminals of the first and second balanced-to-unbalanced transformer circuits are connected to the first and second, and third and fourth input and output terminals, respectively, via first and second balanced line paths, respectively.

摘要翻译： 通过将天线放置在多层布线板上，分别将多路复用器/解复用器电路，第一和第二匹配电路以及第一和第二平衡不平衡变压器电路分别放置在板内，提供高频复合元件，以及 在板的侧表面上提供第一至第四输入和输出端子。 天线经由第一不平衡线路连接到多路复用器/解复用器电路，并且多路复用器/解复用器分别经由第二和第三不平衡线路连接到第一和第二匹配电路。 第一和第二匹配电路分别经由第四和第五不平衡线路路连接到第一和第二平衡不平衡变压器电路。 第一和第二平衡不平衡变压器电路的各个平衡端分别经由第一和第二平衡线路路连接到第一和第二以及第三和第四输入和输出端子。

公开(公告)号：US06599760B2

公开(公告)日：2003-07-29

申请号：US10062564

申请日：2002-02-05

申请人： Toru Watanabe

发明人： Toru Watanabe

IPC分类号： H01L2100

CPC分类号： H01L22/20 ,  H01L21/304 ,  H01L2924/0002 ,  H01L2924/00

摘要： To minimize and stably suppress worsening of a warpage of a wafer in epitaxial treatment. A semiconductor wafer is flattened by a double-sided grinding machine. Machining strains produced at both sides of the semiconductor wafer are removed to measure a direction of the warpage of the semiconductor wafer. The direction of the warpage is adjusted and then, epitaxial treatment is performed.

公开(公告)号：US06124189A

公开(公告)日：2000-09-26

申请号：US818079

申请日：1997-03-14

申请人： Toru Watanabe ,  Katsuya Okumura ,  Katsuhiko Hieda

发明人： Toru Watanabe ,  Katsuya Okumura ,  Katsuhiko Hieda

IPC分类号： H01L29/78 ,  H01L21/336 ,  H01L21/768 ,  H01L21/8234 ,  H01L27/088 ,  H01L21/3205

CPC分类号： H01L29/6659 ,  H01L21/768 ,  H01L29/66545

摘要： A method for forming a metal-strapped polysilicon gate and for simultaneously forming a strapped-metal polysilicon gate and a metal contact filling includes the steps of forming a gate dielectric layer on a surface of a silicon substrate; forming a polysilicon layer on the gate dielectric layer; forming a first insulating layer on the polysilicon layer; forming insulating spacers on either side of the polysilicon layer and the first insulating layer; and forming ion implantation regions in the surface of the silicon substrate. Next, a second insulating layer is deposited on the silicon substrate, and the second insulating layer is polished using chemical mechanical polishing to planarize the upper surface of the second insulating layer with the upper surface of the first insulating layer as a polishing stopper. Then, a contact hole is formed in the second insulating film, wherein the contact hole is laterally spaced from the polysilicon layer and the first insulating layer. Subsequent steps include: removing the first insulating layer, thereby forming an unfilled region above the polysilicon layer; depositing a metal such as tungsten in the unfilled region and the contact hole; and polishing the deposited metal layer to planarize the upper surface of the metal with the upper surface of the second insulating layer.

摘要翻译： 用于形成金属带状多晶硅栅极并用于同时形成带状金属多晶硅栅极和金属接触填充的方法包括以下步骤：在硅衬底的表面上形成栅极电介质层; 在栅介质层上形成多晶硅层; 在所述多晶硅层上形成第一绝缘层; 在所述多晶硅层和所述第一绝缘层的任一侧上形成绝缘间隔物; 以及在所述硅衬底的表面中形成离子注入区。 接下来，在硅衬底上沉积第二绝缘层，并且使用化学机械抛光来抛光第二绝缘层，以使第二绝缘层的上表面与第一绝缘层的上表面平坦化作为抛光停止件。 然后，在第二绝缘膜中形成接触孔，其中接触孔与多晶硅层和第一绝缘层横向隔开。 随后的步骤包括：去除第一绝缘层，从而在多晶硅层上形成未填充区域; 在未填充区域和接触孔中沉积诸如钨的金属; 并且研磨沉积的金属层以使第二绝缘层的上表面平坦化金属的上表面。

公开(公告)号：US5830005A

公开(公告)日：1998-11-03

申请号：US783448

申请日：1997-01-16

申请人： Toru Watanabe

发明人： Toru Watanabe

IPC分类号： H01R4/24 ,  G02B6/38 ,  H01R9/03 ,  H01R13/514 ,  H01R24/00

CPC分类号： G02B6/3887 ,  H01R23/661 ,  H01R12/777 ,  H01R24/64 ,  H01R4/2404

摘要： A modular guide plate for a modular plug having an insulation housing with a receiving cavity includes an organizing section having a plurality of organizing apertures in which core wires of a cable are arranged and held closely in parallel and a plurality of terminal slits through which contact terminals are press-connected to the core wires and an introducing section extending rearwardly from the organizing section and having bottom and side walls for introducing the core wires into the organizing apertures.

摘要翻译： 用于具有具有接收腔的绝缘壳体的模块化插头的模块化引导板包括具有多个组织孔的组织部分，其中电缆的芯线布置并且紧密地保持平行，以及多个端子狭缝，接触端子 被压连接到芯线和从组织部向后延伸的引导部分，并且具有用于将芯线引入组织孔的底侧和侧壁。

公开(公告)号：US5597502A

公开(公告)日：1997-01-28

申请号：US353708

申请日：1994-12-12

申请人： Toru Watanabe ,  Shigetoshi Nagano

发明人： Toru Watanabe ,  Shigetoshi Nagano

IPC分类号： H05B3/00 ,  H05B3/14 ,  H05B3/20 ,  H05B3/46 ,  H05B3/02 ,  A21B1/22 ,  H05B3/34

CPC分类号： H05B3/0019 ,  H05B3/141 ,  H05B3/20

摘要： A single phase and three phase heater element circuit for a ceramic fiber heater wherein a plurality of blocks each of which is formed by a plurality of heater elements arranged side by side on a base of insulation material and connected to one another to form a series circuit, said series circuit being connected across an electric power source, and adjacent ends of the series circuits in adjacent blocks being connected to the same terminal of said electric power source. By connecting adjacent ends of adjacent blocks of ceramic fiber heater element circuits together, the ends of the series circuit connected to separate terminals of the power source are spaced sufficiently far apart from each other such that current flow through the insulation material between ends adjacent the blocks is minimized and preferably substantially prevented for preventing short circuiting and failure of the heater.

摘要翻译： 一种用于陶瓷纤维加热器的单相和三相加热器元件电路，其中多个块由多个加热元件形成，所述多个加热元件并排布置在绝缘材料的基底上并彼此连接以形成串联电路 所述串联电路跨越电源连接，并且相邻块中的串联电路的相邻端连接到所述电源的相同端子。 通过将陶瓷纤维加热器元件电路的相邻块的相邻端连接在一起，连接到电源的分离端子的串联电路的端部彼此间隔足够远，使得电流流过邻近块的端部之间的绝缘材料 被最小化并且优选地基本上被防止以防止加热器的短路和故障。

公开(公告)号：US5547787A

公开(公告)日：1996-08-20

申请号：US49788

申请日：1993-04-21

申请人： Shinichi Ito ,  Haruo Okano ,  Toru Watanabe ,  Katsuya Okumura

发明人： Shinichi Ito ,  Haruo Okano ,  Toru Watanabe ,  Katsuya Okumura

IPC分类号： G03F1/00 ,  G03F1/26 ,  G03F1/32 ,  G03F9/00

CPC分类号： G03F1/32 ,  G03F1/26

摘要： An exposure mask having an excellent alignment accuracy between patterns, which is prepared by first forming on a light transmissive substrate a light shielding film or a semi-transparent film pattern (first pattern) somewhat larger than a desired dimension, forming thereon a semi-transparent film or a light transmissive film pattern (second pattern) so as to include all patterns of the desired dimensions made up of a light shielding part, a semi-transparent part and a light transmissive part, and then removing a projected part of the first pattern with use of the second pattern as a mask.The semi-transparent film is formed of at least two layers each of which contains a common element, thus the semi-transparent film can be made with use of the same apparatus and when patterning, etching process can be carried out with use of the same etchant.Further, since in a mask including the semi-transparent pattern, at least that area of non-pattern zone where light reaches a wafer through the transfer, acts to shield the exposure light, too narrowed pattern or insufficient focal depth can be prevented.

摘要翻译： 通过首先在透光性基板上形成稍大于所需尺寸的遮光膜或半透明膜图案（第一图案）而制成的图案之间具有优异的取向精度的曝光掩模，在其上形成半透明 膜或透光膜图案（第二图案），以便包括由遮光部分，半透明部分和透光部分组成的所需尺寸的所有图案，然后去除第一图案的突出部分 使用第二种图案作为掩模。 半透明膜由至少两层形成，每层均含有共同的元素，因此可以使用相同的装置制造半透明膜，并且当图案化时，可以使用它们进行蚀刻工艺 蚀刻剂 此外，由于在包括半透明图案的掩模中，至少通过转印光到达晶片的非图案区域的区域起着屏蔽曝光光的作用，可以防止太窄的图案或不足的焦深。

公开(公告)号：US5528206A

公开(公告)日：1996-06-18

申请号：US346260

申请日：1994-11-23

申请人： Toru Watanabe

发明人： Toru Watanabe

IPC分类号： H03H9/64

CPC分类号： H03H9/64

摘要： A surface acoustic wave filter includes a piezoelectric substrate. On the surface of the piezoelectric substrate, an input transducer and an output transducer are formed at a predetermined interval. The input transducer and the output transducer are respectively formed with a pair of IDT (interdigital electrode transducers) disposed oppositely. A pair of IDT which construct at least one transducer of the input transducer and the output transducer are formed on the piezoelectric substrate in the following manner. That is, a first impulse train is determined by inverse Fourier transformation of desired transmission characteristics (where, center frequency is f.sub.0 and surface wavelength is .sub.0), a second impulse train is determined by double over-sampling of the first impulse train along its envelope at a half period, wherein the number of unit impulses of the first impulse train is doubled, a third impulse train is determined by dividing the second impulse train into four impulse trains each, among which second and third impulses are made zero, and the IDT are formed on the piezoelectric substrate corresponding to the third impulse train.

摘要翻译： 声表面波滤波器包括压电基片。 在压电基板的表面上，以预定间隔形成输入传感器和输出换能器。 输入传感器和输出传感器分别与相对设置的一对IDT（叉指式电极换能器）形成。 以下述方式在压电基板上形成构成输入变换器和输出变换器的至少一个换能器的一对IDT。 也就是说，通过期望的传输特性（其中，中心频率为f0，表面波长为0）的傅里叶逆变换确定第一脉冲串，第二脉冲串通过沿其信封的第一脉冲串的双重过采样来确定 在半周期中，第一脉冲串的单位脉冲数被加倍，通过将第二脉冲串分成四个脉冲串来确定第三脉冲串，其中第二和第三脉冲为零，并且IDT 形成在与第三脉冲串相对应的压电基板上。

公开(公告)号：US5286185A

公开(公告)日：1994-02-15

申请号：US12073

申请日：1993-02-01

申请人： Yasunori Tashiro ,  Michio Morikawa ,  Torahiko Hayashi ,  Shigeo Uesawa ,  Toru Watanabe

发明人： Yasunori Tashiro ,  Michio Morikawa ,  Torahiko Hayashi ,  Shigeo Uesawa ,  Toru Watanabe

IPC分类号： A21C3/02 ,  A21C11/10 ,  A21C3/06 ,  A21C5/08

CPC分类号： A21C11/103 ,  A21C3/02 ,  Y10S83/932

摘要： An apparatus for manufacturing various shapes of bread that includes a device for forming a continuous sheet of bread dough, a roller for winding up the sheet of bread dough traveling on a horizontal conveyor from one of its sides into a bar of bread dough, the conveyor causing the bar to fall from its downstream end, and a cutter for cutting the falling dough body into dough pieces by squeezing it with flat surfaces of the cutter, according to its preset weight or length.

摘要翻译： 一种用于制造各种形状的面包的装置，其包括用于形成连续的面包面团片的装置，用于将从其一侧的水平输送机上行进的面包面团片卷绕成面包棒的面包的滚筒，输送机 导致杆从其下游端落下;以及切割器，用于根据其预定的重量或长度将切下的面团体通过用切割器的平坦表面挤压而成为面片。

公开(公告)号：USD329842S

公开(公告)日：1992-09-29

申请号：US525394

申请日：1990-05-18

申请人： Toru Watanabe

设计人： Toru Watanabe