公开(公告)号：US20230170350A1

公开(公告)日：2023-06-01

申请号：US18095973

申请日：2023-01-11

Applicant: Intel Corporation

Inventor： Willy RACHMADY ,  Cheng-Ying HUANG ,  Gilbert DEWEY ,  Aaron LILAK ,  Patrick MORROW ,  Anh PHAN ,  Ehren MANNEBACH ,  Jack T. KAVALIEROS

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/66

CPC classification number: H01L27/0886 ,  H01L21/823481 ,  H01L29/66545 ,  H01L21/823431

Abstract: A device is disclosed. The device includes a first semiconductor fin, a first source-drain epitaxial region adjacent a first portion of the first semiconductor fin, a second source-drain epitaxial region adjacent a second portion of the first semiconductor fin, a first gate conductor above the first semiconductor fin, a gate spacer covering the sides of the gate conductor, a second semiconductor fin below the first semiconductor fin, a second gate conductor on a first side of the second semiconductor fin and a third gate conductor on a second side of the second semiconductor fin, a third source-drain epitaxial region adjacent a first portion of the second semiconductor fin, and a fourth source-drain epitaxial region adjacent a second portion of the second semiconductor fin. The device also includes a dielectric isolation structure below the first semiconductor fin and above the second semiconductor fin that separates the first semiconductor fin and the second semiconductor fin.

公开(公告)号：US20220246608A1

公开(公告)日：2022-08-04

申请号：US17726412

申请日：2022-04-21

Applicant: Intel Corporation

Inventor： Aaron D. LILAK ,  Anh PHAN ,  Ehren MANNEBACH ,  Cheng-Ying HUANG ,  Stephanie A. BOJARSKI ,  Gilbert DEWEY ,  Orb ACTON ,  Willy RACHMADY

IPC: H01L27/088 ,  H01L29/423 ,  H01L29/08 ,  H01L21/762 ,  H01L23/528 ,  H01L29/78 ,  H01L29/06

Abstract: Stacked transistor structures having a conductive interconnect between upper and lower transistors. In an embodiment, the interconnect is formed by first provisioning a protective layer over an area to be protected (gate dielectric or other sensitive material) of upper transistor, and then etching material adjacent and below the protected area to expose an underlying contact point of lower transistor. A metal is deposited into the void created by the etch to provide the interconnect. The protective layer is resistant to the etch process and is preserved in the structure, and in some cases may be utilized as a work-function metal. In an embodiment, the protective layer is formed by deposition of reactive semiconductor and metal material layers which are subsequently transformed into a work function metal or work function metal-containing compound. A remnant of unreacted reactive semiconductor material may be left in structure and collinear with protective layer.