公开(公告)号：US20160026912A1

公开(公告)日：2016-01-28

申请号：US14337979

申请日：2014-07-22

Applicant: Intel Corporation

Inventor： Ayose J. Falcon ,  Marc Lupon ,  Enric Herrero Abellanas ,  Pedro Lopez ,  Fernando Latorre ,  Frederico C. Pratas ,  Georgios Tournavitis

IPC: G06N3/06 ,  G06N3/08

CPC classification number: G06N3/06 ,  G06N3/0454 ,  G06N3/063 ,  G06N3/08

Abstract: A processor includes a processor core and a calculation circuit. The processor core includes logic determine a set of weights for use in a convolutional neural network (CNN) calculation and scale up the weights using a scale value. The calculation circuit includes logic to receive the scale value, the set of weights, and a set of input values, wherein each input value and associated weight of a same fixed size. The calculation circuit also includes logic to determine results from convolutional neural network (CNN) calculations based upon the set of weights applied to the set of input values, scale down the results using the scale value, truncate the scaled down results to the fixed size, and communicatively couple the truncated results to an output for a layer of the CNN.

Abstract translation: 处理器包括处理器核心和计算电路。 处理器核心包括确定用于卷积神经网络（CNN）计算的一组权重的逻辑，并使用比例值来放大权重。 计算电路包括接收比例值，权重集合和一组输入值的逻辑，其中每个输入值和相同固定大小的相关权重。 计算电路还包括基于应用于输入值集合的权重集合来确定卷积神经网络（CNN）计算结果的逻辑，使用比例值缩小结果，将缩小的结果截断为固定大小， 并将截断的结果通信地耦合到CNN的层的输出。

公开(公告)号：US20150143057A1

公开(公告)日：2015-05-21

申请号：US13976325

申请日：2013-01-03

Applicant: Intel Corporation

Inventor： Demos Pavlou ,  Pedro Lopez ,  Mirem Hyuseinova ,  Fernando Latorre ,  Steffen Kosinski ,  Ralf Goettsche ,  Varun K. Mohandru

IPC: G06F12/08

CPC classification number: G06F12/0862 ,  G06F9/06 ,  G06F9/30 ,  G06F9/3455 ,  G06F9/383 ,  G06F12/02 ,  G06F2212/6026

Abstract: A system and method for adaptive data prefetching in a processor enables adaptive modification of parameters associated with a prefetch operation. A stride pattern in successive addresses of a memory operation may be detected, including determining a stride length (L). Prefetching of memory operations may be based on a prefetch address determined from a base memory address, the stride length L, and a prefetch distance (D). A number of prefetch misses may be counted at a miss prefetch count (C). Based on the value of the miss prefetch count C, the prefetch distance D may be modified. As a result of adaptive modification of the prefetch distance D, an improved rate of cache hits may be realized.

Abstract translation: 用于处理器中自适应数据预取的系统和方法使得能够对与预取操作相关联的参数进行自适应修改。 可以检测存储器操作的连续地址中的步幅图案，包括确定步幅长度（L）。 存储器操作的预取可以基于从基本存储器地址确定的预取地址，步幅长度L和预取距离（D）。 可以以错误预取计数（C）计数多个预取缺失。 基于缺省预取计数C的值，可以修改预取距离D. 作为预取距离D的自适应修改的结果，可以实现改进的高速缓存命中率。