公开(公告)号：US11289421B2

公开(公告)日：2022-03-29

申请号：US16584666

申请日：2019-09-26

Applicant: Intel Corporation

Inventor： Richard Vreeland ,  Colin Carver ,  William Brezinski ,  Michael Christenson ,  Nafees Kabir

IPC: H01L23/528 ,  H01L23/532 ,  H01L23/00 ,  H01L21/768 ,  H01L21/321 ,  H01L21/3105

Abstract: Composite integrated circuit (IC) device structures that include two components coupled through hybrid bonded interconnect structure. The two components may be two different monolithic IC structures (e.g., chips) that are bonded over a substantially planar dielectric and metallization layer. A surface of a metallization feature may be augmented with supplemental metal, for example to at least partially backfill a recess in a surface of the metallization feature as left by a planarization process. In some exemplary embodiments, supplemental metal is deposited selectively onto a metallization feature through an autocatalytic (electroless) metal deposition process. A surface of a dielectric material surrounding a metallization feature may also be recessed, for example to at least partially neutralize a recess in an adjacent metallization feature, for example resulting from a planarization process.

公开(公告)号：US20210296231A1

公开(公告)日：2021-09-23

申请号：US16824366

申请日：2020-03-19

Applicant: Intel Corporation

Inventor： Elijah Karpov ,  Manish Chandhok ,  Nafees Kabir

IPC: H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L21/768

Abstract: Integrated circuitry comprising devices electrically coupled through a plurality of interconnect levels in which lines of a first and second interconnect level are coupled through a planar slab via. An interconnect line may include a horizontal line segment within one of the first or second interconnect levels, and the slab via may be a vertical line segment between the first and second interconnect levels. A planar slab via may comprise one or more layers of conductive material, which have been deposited upon a planarized substrate material that lacks any features that the conductive material must fill. A planar slab via may be subtractively defined concurrently with a horizontal line of one or both of the first or second interconnect levels.

公开(公告)号：US20210098360A1

公开(公告)日：2021-04-01

申请号：US16586279

申请日：2019-09-27

Applicant: Intel Corporation

Inventor： Manish Chandhok ,  Ramanan Chebiam ,  Brennen Mueller ,  Colin Carver ,  Jeffery Bielefeld ,  Nafees Kabir ,  Richard Vreeland ,  William Brezinski

IPC: H01L23/528 ,  H01L23/535 ,  H01L23/00 ,  H04B1/40

Abstract: An integrated circuit interconnect structure includes a first interconnect in a first metallization level and a first dielectric adjacent to at least a portion of the first interconnect, where the first dielectric having a first carbon content. The integrated circuit interconnect structure further includes a second interconnect in a second metallization level above the first metallization level. The second interconnect includes a lowermost surface in contact with at least a portion of an uppermost surface of the first interconnect. A second dielectric having a second carbon content is adjacent to at least a portion of the second interconnect and the first dielectric. The first carbon concentration increases with distance away from the lowermost surface of the second interconnect and the second carbon concentration increases with distance away from the uppermost surface of the first interconnect.