公开(公告)号：US20210202319A1

公开(公告)日：2021-07-01

申请号：US16728903

申请日：2019-12-27

Applicant: Intel Corporation

Inventor： Ashish Agrawal ,  Gilbert Dewey ,  Cheng-Ying Huang ,  Willy Rachmady ,  Anand Murthy ,  Ryan Keech ,  Cory Bomberger

IPC: H01L21/822 ,  H01L27/12 ,  H01L29/08 ,  H01L23/522 ,  H01L29/417 ,  H01L21/8238

Abstract: A monolithic three-dimensional integrated circuit may include multiple transistor levels separated by one or more levels of metallization. An upper level transistor structure may include monocrystalline source and drain material epitaxially grown from a monocrystalline channel material at a temperature low enough to avoid degradation of a lower level transistor structure and/or degradation of one or more low-k dielectric materials between the transistor levels. A highly conductive n-type silicon source and drain material may be selectively deposited at low temperatures with a high pressure CVD process. Multiple crystals of source drain material arranged in a vertically stacked multi-channel transistor structure may be contacted by a single contact metallization.