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公开(公告)号:US20220058469A1
公开(公告)日:2022-02-24
申请号:US17394671
申请日:2021-08-05
Applicant: Intel Corporation
Inventor: TOMER SCHWARTZ , Ehud Cohen , Uzi Sarel , Amitai Armon , Yaniv Fais , Lev Faivishevsky , Amit Bleiweiss , Yahav Shadmiy , Jacob Subag
Abstract: A mechanism is described for facilitating memory handling and data management in machine learning at autonomous machines. A method of embodiments, as described herein, includes detecting multiple tables associated with multiple neural networks at multiple autonomous machines, where each of the multiple tables include an index. The method may further include combining the multiple tables and multiple indexes associated with the multiple tables into a single table and a single index, respectively, where the single table is communicated to the multiple autonomous machines to allow simultaneous processing of one or more portions of the single table using one or more memory devices and one or more processors of one or more of the multiple autonomous machines.
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公开(公告)号:US11093822B2
公开(公告)日:2021-08-17
申请号:US15499896
申请日:2017-04-28
Applicant: Intel Corporation
Inventor: Uzi Sarel , Ehud Cohen , Tomer Schwartz , Amitai Armon , Yahav Shadmiy , Amit Bleiweiss , Gal Leibovich , Jeremie Dreyfuss , Lev Faivishevsky , Tomer Bar-On , Yaniv Fais , Jacob Subag
Abstract: In an example, an apparatus comprises a plurality of execution units comprising at least a first type of execution unit and a second type of execution unit and logic, at least partially including hardware logic, to expose embedded cast operations in at least one of a load instruction or a store instruction; determine a target precision level for the cast operations; and load the cast operations at the target precision level. Other embodiments are also disclosed and claimed.
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公开(公告)号:US20210141604A1
公开(公告)日:2021-05-13
申请号:US17103179
申请日:2020-11-24
Applicant: Intel Corporation
Inventor: Yaniv Fais , Tomer Bar-On , Jacob Subag , Jeremie Dreyfuss , Lev Faivishevsky , Michael Behar , Amit Bleiweiss , Guy Jacob , Gal Leibovich , Itamar Ben-Ari , Galina Ryvchin , Eyal Yaacoby
Abstract: In an example, an apparatus comprises a plurality of execution units and logic, at least partially including hardware logic, to gate at least one of a multiply unit or an accumulate unit in response to an input of value zero. Other embodiments are also disclosed and claimed.
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公开(公告)号:US10963783B2
公开(公告)日:2021-03-30
申请号:US15436841
申请日:2017-02-19
Applicant: INTEL CORPORATION
Inventor: Lev Faivishevsky , Amitai Armon
Abstract: Technologies for optimization of machine learning training include a computing device to train a machine learning network with a training algorithm that is configured with configuration parameters. The computing device may perform many training instances in parallel. The computing device captures a time series of partial accuracy values from the training. Each partial accuracy value is indicative of machine learning network accuracy at an associated training iteration. The computing device inputs the configuration parameters to a feed-forward neural network to generate a representation and inputs the representation to a recurrent neural network. The computing device trains the feed-forward neural network and the recurrent neural network against the partial accuracy values. The computing device optimizes the feed-forward neural network and the recurrent neural network to determine optimized configuration parameters. The optimized configuration parameters may minimize training time to achieve a predetermined accuracy level. Other embodiments are described and claimed.
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公开(公告)号:US10606559B2
公开(公告)日:2020-03-31
申请号:US16439174
申请日:2019-06-12
Applicant: INTEL CORPORATION
Inventor: Yaniv Fais , Tomer Bar-On , Jacob Subag , Jeremie Dreyfuss , Lev Faivishevsky , Michael Behar , Amit Bleiweiss , Guy Jacob , Gal Leibovich , Itamar Ben-Ari , Galina Ryvchin , Eyal Yaacoby
Abstract: In an example, an apparatus comprises a plurality of execution units and logic, at least partially including hardware logic, to gate at least one of a multiply unit or an accumulate unit in response to an input of value zero. Other embodiments are also disclosed and claimed.
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公开(公告)号:US20180307982A1
公开(公告)日:2018-10-25
申请号:US15494887
申请日:2017-04-24
Applicant: Intel Corporation
Inventor: Lev Faivishevsky , Tomer Bar-On , Yaniv Fais , Jacob Subag , Jeremie Dreyfuss , Amit Bleiweiss , Tomer Schwartz
CPC classification number: G06N3/08 , G06N99/005 , G06T1/20
Abstract: In an example, an apparatus comprises a plurality of execution units comprising and logic, at least partially including hardware logic, to receive a plurality of data inputs for training a neural network, wherein the data inputs comprise training data and weights inputs; represent the data inputs in a first form; and represent the weight inputs in a second form. Other embodiments are also disclosed and claimed.
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公开(公告)号:US20180240010A1
公开(公告)日:2018-08-23
申请号:US15436841
申请日:2017-02-19
Applicant: INTEL CORPORATION
Inventor: Lev Faivishevsky , Amitai Armon
CPC classification number: G06N3/08 , G06N3/0445 , G06N3/0454
Abstract: Technologies for optimization of machine learning training include a computing device to train a machine learning network with a training algorithm that is configured with configuration parameters. The computing device may perform many training instances in parallel. The computing device captures a time series of partial accuracy values from the training. Each partial accuracy value is indicative of machine learning network accuracy at an associated training iteration. The computing device inputs the configuration parameters to a feed-forward neural network to generate a representation and inputs the representation to a recurrent neural network. The computing device trains the feed-forward neural network and the recurrent neural network against the partial accuracy values. The computing device optimizes the feed-forward neural network and the recurrent neural network to determine optimized configuration parameters. The optimized configuration parameters may minimize training time to achieve a predetermined accuracy level. Other embodiments are described and claimed.
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公开(公告)号:US20160095013A1
公开(公告)日:2016-03-31
申请号:US14579083
申请日:2014-12-22
Applicant: Intel Corporation
Inventor: Lev Faivishevsky , Amitai Armon
CPC classification number: H04W28/021 , G08C25/00 , H04L67/12 , H04L67/125 , H04Q9/00 , H04W28/08 , H04W84/18
Abstract: Examples of systems and methods for multisensory change detection are generally described herein. A method may include receiving a first set of signals from a first combination of sensors and a second set of signals from a second combination of sensors in a plurality of sensors, and determining a first distribution for the first set of signals and a second distribution for the second set of signals. The method may include estimating a divergence between the first and second distributions using the first and second combinations of sensors, a count of the plurality of sensors, and distances from a plurality of signals in the second set of signals to a first plurality of nearest neighbor signals in the first set of signals and a second plurality of nearest neighbor signals in the second set of signals. The method may include determining whether the divergence exceeds a threshold.
Abstract translation: 这里通常描述用于多感觉变化检测的系统和方法的示例。 一种方法可以包括从传感器的第一组合和来自多个传感器中的传感器的第二组合的第二组信号接收第一组信号,以及确定第一组信号的第一分布,以及用于 第二组信号。 该方法可以包括使用传感器的第一和第二组合,多个传感器的计数以及从第二组信号中的多个信号到第一多个最近邻的距离来估计第一和第二分布之间的发散度 第一组信号中的信号和第二组信号中的第二多个最近邻信号。 该方法可以包括确定发散是否超过阈值。
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公开(公告)号:US20240419956A1
公开(公告)日:2024-12-19
申请号:US18749806
申请日:2024-06-21
Applicant: Intel Corporation
Inventor: Eran Ben-Avi , Neta Zmora , Guy Jacob , Lev Faivishevsky , Jeremie Dreyfuss , Tomer Bar-On , Jacob Subag , Yaniv Fais , Shira Hirsch , Orly Weisel , Zigi Walter , Yarden Oren
Abstract: In an example, an apparatus comprises a plurality of execution units comprising and logic, at least partially including hardware logic, to traverse a solution space, score a plurality of solutions to a scheduling deep learning network execution, and select a preferred solution from the plurality of solutions to implement the deep learning network. Other embodiments are also disclosed and claimed.
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公开(公告)号:US20240112033A1
公开(公告)日:2024-04-04
申请号:US18514069
申请日:2023-11-20
Applicant: Intel Corporation
Inventor: Amit Bleiweiss , Itamar Ben-Ari , Michael Behar , Guy Jacob , Gal Leibovich , Jacob Subag , Lev Faivishevsky , Yaniv Fais , Tomer Schwartz
CPC classification number: G06N3/082 , G06F8/52 , G06F9/44552 , G06N3/04 , G06N3/105 , G06N5/04 , G06N3/084
Abstract: In an example, an apparatus comprises at least one execution platform; and logic, at least partially including hardware logic, to receive a trained neural network model in a model optimizer and convert the trained neural network model to an optimized model comprising parameters that are fit to the at least one execution platform. Other embodiments are also disclosed and claimed.
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