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1.发明授权公开(公告)号：US09424620B2
公开(公告)日：2016-08-23
申请号：US13730908
申请日：2012-12-29
Applicant: Intel Corporation
Inventor： Idan Mondjak , Supratik Majumder , Eyal Yaacoby
CPC classification number: G06T1/20 , G06F1/3206 , G06F1/324 , G06F1/325 , G09G5/363 , G09G2330/021 , G09G2360/08 , G09G2360/121 , Y02D10/126
Abstract: A method performed by a processor is described. The method may include identifying a graphics processing unit (GPU) phase of a frame, using said identified GPU phase to obtain frequency scalability information for said identified GPU phase, and determining whether to change a frequency at which a GPU is to draw said frame within said phase based on said frequency scalability information.
Abstract translation: 描述由处理器执行的方法。 该方法可以包括使用所识别的GPU相位来识别帧的图形处理单元（GPU）相位，以获得用于所述所识别的GPU相位的频率可伸缩性信息，以及确定是否改变GPU在其中绘制所述帧的频率 所述相位基于所述频率可伸缩性信息。
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公开(公告)号：US10853035B2
公开(公告)日：2020-12-01
申请号：US16833128
申请日：2020-03-27
Applicant: Intel Corporation
Inventor： Yaniv Fais , Tomer Bar-On , Jacob Subag , Jeremie Dreyfuss , Lev Faivishevsky , Michael Behar , Amit Bleiweiss , Guy Jacob , Gal Leibovich , Itamar Ben-Ari , Galina Ryvchin , Eyal Yaacoby
Abstract: In an example, an apparatus comprises a plurality of execution units and logic, at least partially including hardware logic, to gate at least one of a multiply unit or an accumulate unit in response to an input of value zero. Other embodiments are also disclosed and claimed.
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公开(公告)号：US10372416B2
公开(公告)日：2019-08-06
申请号：US15499893
申请日：2017-04-28
Applicant: Intel Corporation
Inventor： Yaniv Fais , Tomer Bar-On , Jacob Subag , Jeremie Dreyfuss , Lev Faivishevsky , Michael Behar , Amit Bleiweiss , Guy Jacob , Gal Leibovich , Itamar Ben-Ari , Galina Ryvchin , Eyal Yaacoby
Abstract: In an example, an apparatus comprises a plurality of execution units and logic, at least partially including hardware logic, to gate at least one of a multiply unit or an accumulate unit in response to an input of value zero. Other embodiments are also disclosed and claimed.
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Patent Agency Ranking">
公开(公告)号：US20200293282A1
公开(公告)日：2020-09-17
申请号：US16833128
申请日：2020-03-27
Applicant: Intel Corporation
Inventor： YANIV Fais , Tomer Bar-On , Jacob Subag , Jeremie Dreyfuss , Lev Faivishevsky , Michael Behar , Amit Bleiweiss , Guy Jacob , Gal Leibovich , Itamar Ben-Ari , Galina Ryvchin , Eyal Yaacoby
Abstract: In an example, an apparatus comprises a plurality of execution units and logic, at least partially including hardware logic, to gate at least one of a multiply unit or an accumulate unit in response to an input of value zero. Other embodiments are also disclosed and claimed.
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公开(公告)号：US20180314492A1
公开(公告)日：2018-11-01
申请号：US15499893
申请日：2017-04-28
Applicant: Intel Corporation
Inventor： Yaniv Fais , Tomer Bar-On , Jacob Subag , Jeremie Dreyfuss , Lev Faivishevsky , Michael Behar , Amit Bleiweiss , Guy Jacob , Gal Leibovich , Itamar Ben-Ari , Galina Ryvchin , Eyal Yaacoby
CPC classification number: G06F7/5332 , G06N20/00 , G06T1/20
Abstract: In an example, an apparatus comprises a plurality of execution units and logic, at least partially including hardware logic, to gate at least one of a multiply unit or an accumulate unit in response to an input of value zero. Other embodiments are also disclosed and claimed.
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公开(公告)号：US11656846B2
公开(公告)日：2023-05-23
申请号：US17103179
申请日：2020-11-24
Applicant: Intel Corporation
Inventor： Yaniv Fais , Tomer Bar-On , Jacob Subag , Jeremie Dreyfuss , Lev Faivishevsky , Michael Behar , Amit Bleiweiss , Guy Jacob , Gal Leibovich , Itamar Ben-Ari , Galina Ryvchin , Eyal Yaacoby
CPC classification number: G06F7/5332 , G06N20/00 , G06T1/20
Abstract: In an example, an apparatus comprises a plurality of execution units and logic, at least partially including hardware logic, to gate at least one of a multiply unit or an accumulate unit in response to an input of value zero. Other embodiments are also disclosed and claimed.
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公开(公告)号：US20210141604A1
公开(公告)日：2021-05-13
申请号：US17103179
申请日：2020-11-24
Applicant: Intel Corporation
Inventor： Yaniv Fais , Tomer Bar-On , Jacob Subag , Jeremie Dreyfuss , Lev Faivishevsky , Michael Behar , Amit Bleiweiss , Guy Jacob , Gal Leibovich , Itamar Ben-Ari , Galina Ryvchin , Eyal Yaacoby
Abstract: In an example, an apparatus comprises a plurality of execution units and logic, at least partially including hardware logic, to gate at least one of a multiply unit or an accumulate unit in response to an input of value zero. Other embodiments are also disclosed and claimed.
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公开(公告)号：US10606559B2
公开(公告)日：2020-03-31
申请号：US16439174
申请日：2019-06-12
Applicant: INTEL CORPORATION
Inventor： Yaniv Fais , Tomer Bar-On , Jacob Subag , Jeremie Dreyfuss , Lev Faivishevsky , Michael Behar , Amit Bleiweiss , Guy Jacob , Gal Leibovich , Itamar Ben-Ari , Galina Ryvchin , Eyal Yaacoby
Abstract: In an example, an apparatus comprises a plurality of execution units and logic, at least partially including hardware logic, to gate at least one of a multiply unit or an accumulate unit in response to an input of value zero. Other embodiments are also disclosed and claimed.
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