公开(公告)号：US09568547B2

公开(公告)日：2017-02-14

申请号：US14659850

申请日：2015-03-17

Applicant: Intel Corporation

Inventor： Sankaran M. Menon ,  Babu TRP ,  Rolf Kuehnis

IPC: G06F11/36 ,  G01R31/317 ,  G01R31/3177 ,  G06F11/34

CPC classification number: G01R31/31718 ,  G01R31/31705 ,  G01R31/3177 ,  G06F11/3466 ,  G06F11/3476 ,  G06F11/348 ,  G06F11/3648 ,  G06F2201/88 ,  Y02D10/34

Abstract: In one embodiment, a bandwidth management controller is coupled to a debug interconnect to dynamically allocate buffer space of a plurality of data buffers to hardware trace information, software trace information, and firmware trace information. The bandwidth management controller further includes a control logic to dynamically control at least one of a voltage and a frequency of the debug interconnect based at least in part on a debug activity level or a functional activity level. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，带宽管理控制器耦合到调试互连以动态地将多个数据缓冲器的缓冲空间分配给硬件跟踪信息，软件跟踪信息和固件跟踪信息。 带宽管理控制器还包括控制逻辑，用于至少部分地基于调试活动级别或功能活动级别来动态地控制调试互连的电压和频率中的至少一个。 描述和要求保护其他实施例。

公开(公告)号：US20160259005A1

公开(公告)日：2016-09-08

申请号：US14669693

申请日：2015-03-26

Applicant: Intel Corporation

Inventor： Sankaran M. Menon ,  Rolf Kuehnis

IPC: G01R31/317 ,  G01R31/3177

CPC classification number: G01R31/31705 ,  G01R31/3177 ,  G06F11/364

Abstract: Techniques of debugging a computing system are described herein. The techniques may include an apparatus having an all-in-one port. The all-in-one port may include a configuration channel and a sideband channel. The sideband channel is configured to default to a debug mode when the configuration channel is not communicatively coupled to an external device.

Abstract translation: 这里描述了调试计算系统的技术。 这些技术可以包括具有一体化端口的装置。 一体化端口可以包括配置信道和边带信道。 当配置通道不通信地耦合到外部设备时，边带通道被配置为默认为调试模式。