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公开(公告)号：US20240111701A1
公开(公告)日：2024-04-04
申请号：US18539063
申请日：2023-12-13
Applicant: Intel Corporation
Inventor： Aruni P. Nelson , Enrico David Carrieri , Rolf Kuehnis , Peter Onufryk , Sridhar Muthrasanallur
CPC classification number: G06F13/4031 , G06F13/225 , G06F13/4221
Abstract: Embodiments herein relate to a universal component interconnect express (UCIe) link that includes a mainband and a sideband. One or more pieces of logic may identify a data that is to be transmitted on the sideband. The logic may then identify, based on factors such as a characteristic of the data or a characteristic of the link, whether to transmit the data on the mainband. Other embodiments may be described and/or claimed.
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公开(公告)号：US20230315192A1
公开(公告)日：2023-10-05
申请号：US18296560
申请日：2023-04-06
Applicant: Intel Corporation
Inventor： Rolf Kuehnis , Matthew Long , Julien Sebot
IPC: G06F1/3296 , G01K7/02 , H03K17/082
CPC classification number: G06F1/3296 , G01K7/021 , H03K17/082
Abstract: In one embodiment, a processor includes: a first plurality of intellectual property (IP) circuits to execute operations; and a second plurality of integrated voltage regulators, where the second plurality of integrated voltage regulators are oversubscribed with respect to the first plurality of IP circuits. Other embodiments are described and claimed.
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公开(公告)号：US11157374B2
公开(公告)日：2021-10-26
申请号：US16234671
申请日：2018-12-28
Applicant: Intel Corporation
Inventor： Sankaran M. Menon , Rolf Kuehnis
Abstract: Technologies for efficiently providing reliable compute operations for mission critical applications include a reliability management system. The reliability management system includes circuitry configured to obtain conclusion data indicative of a conclusion made by each of two or fewer compute devices of a host system. The conclusion data from each compute device pertains to the same operation. Additionally, the circuitry is configured to identify whether an error has occurred in the operation of each compute device, determine, in response to a determination that an error has occurred, a severity of the error, and cause the host system to perform a responsive action as a function of the determined severity of the error.
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公开(公告)号：US10088514B2
公开(公告)日：2018-10-02
申请号：US14979243
申请日：2015-12-22
Applicant: Intel Corporation
Inventor： Rolf Kuehnis , Robert A. Dunstan
IPC: G06F3/00 , G01R31/04 , G06F9/4401 , G06F13/40
Abstract: Techniques described herein include a method, system, and apparatus for detecting an orientation configuration. For example, an apparatus having an all-in-one port may include a first configuration pin and a second configuration pin. The apparatus may also include logic configured to enter into an accessory mode based on a presence of a first signal on the first configuration pin and a second signal on the second configuration pin. The logic may be further configured to provide an orientation indication by altering the first signal on the first configuration pin.
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公开(公告)号：US09535117B2
公开(公告)日：2017-01-03
申请号：US14669693
申请日：2015-03-26
Applicant: Intel Corporation
Inventor： Sankaran M. Menon , Rolf Kuehnis
IPC: G06F11/00 , G01R31/317 , G01R31/3177
CPC classification number: G01R31/31705 , G01R31/3177 , G06F11/364
Abstract: Techniques of debugging a computing system are described herein. The techniques may include an apparatus having an all-in-one port. The all-in-one port may include a configuration channel and a sideband channel. The sideband channel is configured to default to a debug mode when the configuration channel is not communicatively coupled to an external device.
Abstract translation: 这里描述了调试计算系统的技术。 这些技术可以包括具有一体化端口的装置。 一体化端口可以包括配置信道和边带信道。 当配置通道不通信地耦合到外部设备时，边带通道被配置为默认为调试模式。
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Patent Agency Ranking
公开(公告)号：US11656676B2
公开(公告)日：2023-05-23
申请号：US16217312
申请日：2018-12-12
Applicant: Intel Corporation
Inventor： Rolf Kuehnis , Matthew Long , Julien Sebot
IPC: G06F1/32 , G06F1/3296 , G01K7/02 , H03K17/082
CPC classification number: G06F1/3296 , G01K7/021 , H03K17/082
Abstract: In one embodiment, a processor includes: a first plurality of intellectual property (IP) circuits to execute operations; and a second plurality of integrated voltage regulators, where the second plurality of integrated voltage regulators are oversubscribed with respect to the first plurality of IP circuits. Other embodiments are described and claimed.
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公开(公告)号：US10901871B2
公开(公告)日：2021-01-26
申请号：US16292850
申请日：2019-03-05
Applicant: Intel Corporation
Inventor： Rolf Kuehnis , Peter Lachner
Abstract: In one embodiment, an apparatus includes: a first trace source to generate a plurality of first trace messages and a first local platform description identifier to identify the first trace source; a second trace source to generate a plurality of second trace messages and a second local platform description identifier to identify the second trace source; and a trace aggregator coupled to the first and the second trace sources, the trace aggregator to generate a global platform description identifier for the apparatus and output a trace stream including the global platform destination identifier, the first and second local platform description identifiers, the plurality of first trace messages and the plurality of second trace messages. Other embodiments are described and claimed.
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公开(公告)号：US10795399B2
公开(公告)日：2020-10-06
申请号：US15855381
申请日：2017-12-27
Applicant: Intel Corporation
Inventor： Patrik Eder , Rolf Kuehnis , Enrico Carrieri
IPC: G06F1/12 , G06F1/08 , G01R31/317 , G06F13/40 , G06F13/42 , G06F13/00 , G06F1/10 , H04L7/10 , H04J3/06 , H04L7/00
Abstract: One embodiment provides a master device in a bus system. The master device includes bus interface circuitry to exchange commands and data with a slave device in communication with the master device; and test sequence generation logic to generate at least one test sequence, each test sequence having a corresponding unique clock signal having a unique clock frequency; the test sequence generation logic also to transmit the at least one test sequence and the corresponding unique clock signal to the slave device; the test signal generation logic also to determine, based on feedback from the slave device, if the slave device is capable of communicating with the master device using the unique clock frequency.
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公开(公告)号：US10733077B2
公开(公告)日：2020-08-04
申请号：US15856427
申请日：2017-12-28
Applicant: INTEL CORPORATION
Inventor： Sankaran Menon , Krishna Kumar Ganesan , Rolf Kuehnis , Eija Maarit Hillevi Manninen
Abstract: Techniques and apparatus for error and performance analysis of a computing device are described. In one embodiment, for example, an apparatus may include at least one memory and logic coupled to the at least one memory, wherein the logic is further to access at least one trace associated with at least one trace source, access timing information associated with the at least one trace, generate a plurality of waypoints for at least one trace, each of the plurality of waypoints comprising a step of at least one trace and a time stamp, and generate at least one performance benchmark log for the at least one trace, the at least one benchmark log comprising a plurality of benchmark waypoints corresponding to the plurality of waypoints.
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10.发明申请公开(公告)号：US20190138408A1
公开(公告)日：2019-05-09
申请号：US16234671
申请日：2018-12-28
Applicant: Intel Corporation
Inventor： Sankaran M. Menon , Rolf Kuehnis
IPC: G06F11/18
Abstract: Technologies for efficiently providing reliable compute operations for mission critical applications include a reliability management system. The reliability management system includes circuitry configured to obtain conclusion data indicative of a conclusion made by each of two or fewer compute devices of a host system. The conclusion data from each compute device pertains to the same operation. Additionally, the circuitry is configured to identify whether an error has occurred in the operation of each compute device, determine, in response to a determination that an error has occurred, a severity of the error, and cause the host system to perform a responsive action as a function of the determined severity of the error.
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