公开(公告)号：US6078057A

公开(公告)日：2000-06-20

申请号：US10881

申请日：1998-01-22

申请人： David P. Vallett

发明人： David P. Vallett

IPC分类号： G01R31/28 ,  H01L23/58 ,  H01L29/40

CPC分类号： H01L22/32 ,  G01R31/2884

摘要： Integrated circuits are provided which permit backside probing while being operated. Conductive trenches are fabricated into the surface of semiconductor chip at preselected locations. Access to specific electrically connected nodes of the integrated circuit can be effected through the conductive trenches by backside thinning and milling of the semiconductor chip followed by e-beam probe or mechanical probe usage.

公开(公告)号：US6010392A

公开(公告)日：2000-01-04

申请号：US24912

申请日：1998-02-17

申请人： Richard J. Evans ,  Philip S. Phoenix ,  David P. Vallett

发明人： Richard J. Evans ,  Philip S. Phoenix ,  David P. Vallett

IPC分类号： B24B37/30 ,  B24B41/06

CPC分类号： B24B37/30

摘要： A fixture for holding a semiconductor die against an abrasive media for the purpose of thinning the die is described. The fixture provides means for aligning the back of the die to a reference plane that is coplanar with the plane of the abrasive and is in contact with the abrasive media during the thinning process.

摘要翻译： 描述了用于将半导体管芯保持在研磨介质上以用于使管芯变薄的夹具。 夹具提供了将模具的背面与研磨平面共面的参考平面对准的装置，并且在稀化过程中与磨料介质接触。

公开(公告)号：US07285860B2

公开(公告)日：2007-10-23

申请号：US11277663

申请日：2006-03-28

申请人： John M. Cohn ,  Leah Marie P. Pastel ,  Thomas G. Sopchak ,  David P. Vallett

发明人： John M. Cohn ,  Leah Marie P. Pastel ,  Thomas G. Sopchak ,  David P. Vallett

IPC分类号： H01L23/48

CPC分类号： G01R31/2884 ,  G01R31/307 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for implementing defect inspection of an integrated circuit includes configuring a power bus grid structure on a first metal interconnect level, the power bus grid structure including a first plurality of wire pairs. The first plurality of wire pairs is arranged in a manner such that a first wire in each of the first plurality of wire pairs is electrically coupled to conductive structures beneath the first metal interconnect level, and a second wire in each of the first plurality of wire pairs is initially electrically isolated from the conductive structures beneath the first metal interconnect level. The first wire in each of the first plurality of wire pairs is biased to a known voltage, and a charge contrast inspection is performed between the first wire and the second wire of each of the first plurality of wire pairs.

摘要翻译： 用于实现集成电路的缺陷检查的方法包括在第一金属互连级上配置电力总线栅格结构，所述电力总线栅格结构包括第一多个线对。 第一组多个线对被布置成使得第一多个线对中的每一个中的第一线电耦合到第一金属互连水平面下方的导电结构，并且在第一多个线中的每一个中的第二线 对最初与第一金属互连层下面的导电结构电隔离。 第一多个线对中的每一个中的第一线被偏置到已知电压，并且在第一多个线对中的每一个的第一线和第二线之间执行电荷对比度检查。

公开(公告)号：US07240322B2

公开(公告)日：2007-07-03

申请号：US10907494

申请日：2005-04-04

申请人： James W. Adkisson ,  Greg Bazan ,  John M. Cohn ,  Matthew S. Grady ,  Thomas G. Sopchak ,  David P. Vallett

发明人： James W. Adkisson ,  Greg Bazan ,  John M. Cohn ,  Matthew S. Grady ,  Thomas G. Sopchak ,  David P. Vallett

IPC分类号： G06F17/50

CPC分类号： H01L22/20 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit, a method and a system for designing and a method fabricating the integrated circuit. The method including: (a) generating a photomask level design of an integrated circuit design of the integrated circuit, the photomask level design comprising a multiplicity of integrated circuit element shapes; (b) designating regions of the photomask level design between adjacent integrated circuit element shapes, the designated regions large enough to require placement of fill shapes between the adjacent integrated circuit elements based on fill shape rules, the fill shapes not required for the operation of the integrated circuit; and (c) placing one or more monitor structure shapes of a monitor structure in at least one of the designated regions, the monitor structure not required for the operation of the integrated circuit.

摘要翻译： 一种用于设计的集成电路，方法和系统以及制造集成电路的方法。 该方法包括：（a）生成集成电路的集成电路设计的光掩模级设计，光掩模级设计包括多个集成电路元件形状; （b）指定相邻集成电路元件形状之间的光掩模级设计的区域，指定区域足够大以至于基于填充形状规则需要在相邻集成电路元件之间放置填充形状， 集成电路; 以及（c）将监视器结构的一个或多个监视器结构形状放置在指定区域中的至少一个中，该集成电路的操作不需要监视器结构。

公开(公告)号：US5990562A

公开(公告)日：1999-11-23

申请号：US806570

申请日：1997-02-25

申请人： David P. Vallett

发明人： David P. Vallett

IPC分类号： G01R31/28 ,  H01L23/58 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L22/32 ,  G01R31/2884

摘要： Integrated circuits are provided which permit backside probing while being operated. Conductive trenches are fabricated into the surface of semiconductor chip at preselected locations. Access to specific electrically connected nodes of the integrated circuit can be effected through the conductive trenches by backside thinning and milling of the semiconductor chip followed by e-beam probe or mechanical probe usage.