公开(公告)号：US06528838B1

公开(公告)日：2003-03-04

申请号：US10012296

申请日：2001-11-13

申请人： Chit Hwei Ng ,  Chaw Sing Ho

发明人： Chit Hwei Ng ,  Chaw Sing Ho

IPC分类号： H01L27108

CPC分类号： H01L28/82 ,  H01L28/55

摘要： In one method embodiment, the present invention recites forming an opening in a substrate during a damascene process. The present embodiment then recites forming a dielectric region having two curvilinear surfaces opposite one another at least partially within the opening during the damascene process. The surfaces are curvilinear with respect to a horizontal cross-section. The present embodiment then recites forming a first copper region having a curvilinear surface proximate one of the surfaces of the dielectric region during the damascene process. The present embodiment then recites forming a second copper region having a curvilinear surface proximate a second surface of the dielectric region during the damascene process. In so doing, the dielectric region forms a dielectric barrier between the first copper region and the second copper region such that the vertical cylindrical MIM capacitor is formed.

摘要翻译： 在一个方法实施例中，本发明在镶嵌工艺期间背景在衬底中形成开口。 本实施例然后在镶嵌过程期间至少部分地在开口内形成具有彼此相对的两个曲线表面的电介质区域。 表面相对于水平横截面是曲线的。 然后，本实施例在镶嵌过程期间形成具有靠近电介质区域的一个表面的曲线表面的第一铜区域。 然后，本实施例在镶嵌过程期间叙述形成具有靠近电介质区域的第二表面的曲线表面的第二铜区域。 这样，电介质区域在第一铜区域和第二铜区域之间形成电介质阻挡层，从而形成垂直圆柱形MIM电容器。

公开(公告)号：US06670237B1

公开(公告)日：2003-12-30

申请号：US10209729

申请日：2002-08-01

申请人： Wye Boon Loh ,  Chit Hwei Ng

发明人： Wye Boon Loh ,  Chit Hwei Ng

IPC分类号： H01L218242

CPC分类号： H01L28/40 ,  H01L21/76838 ,  H01L23/5223 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for forming a capacitor in a semiconductor device. An embodiment simultaneously forms a MIM capacitor and a dual damascene interconnect using common process steps. An embodiment comprises: forming a capacitor bottom plate and a first metal line over the semiconductor structure. We form a second dielectric layer over the capacitor bottom plate, the first metal line, and a first dielectric layer. Next, we form a top plate opening in the second dielectric layer to at least partially expose the capacitor bottom plate. A capacitor dielectric layer is formed over the capacitor bottom plate and the second dielectric layer. A capacitor top plate is formed in the top plate opening. Subsequently, we form a via opening through at least the second dielectric layer, the capacitor dielectric layer over the first metal line to expose a portion of the first metal line. Next, we fill the via opening with a second metal layer to form a via plug. A third dielectric layer is formed over the via plug and the capacitor top plate. We form a first trench opening and a second trench opening through the third dielectric layer, the second passivation layer and the third passivation layer. The first trench opening exposes a portion of the capacitor top plate. The second trench opening exposes a portion of the via plug. Next, we form a first trench plug in first trench opening and a second trench plug is the second trench opening. The top plate, the capacitor dielectric and the bottom plate form a capacitor.

摘要翻译： 一种在半导体器件中形成电容器的方法。 一个实施例同时使用常规的工艺步骤形成MIM电容器和双镶嵌互连。 一个实施例包括：在半导体结构上形成电容器底板和第一金属线。 我们在电容器底板，第一金属线和第一介电层之上形成第二电介质层。 接下来，我们在第二电介质层中形成顶板开口以至少部分地暴露电容器底板。 在电容器底板和第二电介质层上形成电容器电介质层。 在顶板开口中形成电容器顶板。 随后，我们通过至少第二电介质层，第一金属线上的电容器电介质层形成通孔，以露出第一金属线的一部分。 接下来，我们用通孔开口填充第二金属层以形成通孔塞。 在通孔插头和电容器顶板之上形成第三电介质层。 我们形成通过第三介电层，第二钝化层和第三钝化层的第一沟槽开口和第二沟槽开口。 第一沟槽开口露出电容器顶板的一部分。 第二沟槽开口暴露通孔塞的一部分。 接下来，我们在第一沟槽开口中形成第一沟槽塞，第二沟槽塞是第二沟槽开口。 顶板，电容器电介质和底板形成电容器。

公开(公告)号：US06548367B1

公开(公告)日：2003-04-15

申请号：US10120105

申请日：2002-04-09

申请人： Chit Hwei Ng ,  Chaw Sing Ho

发明人： Chit Hwei Ng ,  Chaw Sing Ho

IPC分类号： H01L2120

CPC分类号： H01L28/82 ,  H01L28/55

摘要： In one method embodiment, the present invention recites forming an opening in a substrate during a damascene process. The present embodiment then recites forming a dielectric region having two curvilinear surfaces opposite one another at least partially within the opening during the damascene process. The surfaces are curvilinear with respect to a horizontal cross-section. The present embodiment then recites forming a first copper region having a curvilinear surface proximate one of the surfaces of the dielectric region during the damascene process. The present embodiment then recites forming a second copper region having a curvilinear surface proximate a second surface of the dielectric region during the damascene process. In so doing, the dielectric region forms a dielectric barrier between the first copper region and the second copper region such that the vertical cylindrical MIM capacitor is formed.

摘要翻译： 在一个方法实施例中，本发明在镶嵌工艺期间背景在衬底中形成开口。 本实施例然后在镶嵌过程期间至少部分地在开口内形成具有彼此相对的两个曲线表面的电介质区域。 表面相对于水平横截面是曲线的。 然后，本实施例在镶嵌过程期间形成具有靠近电介质区域的一个表面的曲线表面的第一铜区域。 然后，本实施例在镶嵌过程期间叙述形成具有靠近电介质区域的第二表面的曲线表面的第二铜区域。 这样，电介质区域在第一铜区域和第二铜区域之间形成电介质阻挡层，从而形成垂直圆柱形MIM电容器。

公开(公告)号：US06410376B1

公开(公告)日：2002-06-25

申请号：US09797555

申请日：2001-03-02

申请人： Chit Hwei Ng ,  Chaw Sing Ho

发明人： Chit Hwei Ng ,  Chaw Sing Ho

IPC分类号： H01L218238

CPC分类号： H01L21/823878 ,  H01L21/823842

摘要： A new method for forming a dual-metal gate CMOS transistors is described. An NMOS and a PMOS active area of a semiconductor substrate are separated by isolation regions. A nitride layer is deposited overlying a gate dielectric layer and patterned to form a first dummy gate in each of the active areas. First ions are implanted to form source/drain regions in each of the active areas not covered by the first dummy gates. The first dummy gates are isotropically etched to form second dummy gates thinner than the first dummy gates. Second ions are implanted to form lightly doped source/drain regions in each of the active areas not covered by the second dummy gates. Dielectric spacers are formed on sidewalls of the second dummy gates and the source/drain regions are silicided. A dielectric layer is deposited and planarized to the second dummy gates. Thereafter, the second dummy gates are removed, leaving gate openings in the dielectric layer. A mask is formed over the PMOS active area. A first metal layer is deposited in the gate opening in the NMOS active area and planarized to the mask. The mask is removed. A second metal layer is deposited in the gate opening in the PMOS active area. The first and second metal layers are polished away to the dielectric layer thereby completing formation of dual-metal gate CMOS transistors in the fabrication of an integrated circuit.

摘要翻译： 描述了形成双金属栅极CMOS晶体管的新方法。 半导体衬底的NMOS和PMOS有源区由隔离区隔开。 沉积覆盖在栅极电介质层上的氮化物层并且被图案化以在每个有源区域中形成第一伪栅极。 植入第一离子以在未被第一伪栅极覆盖的每个有源区域中形成源极/漏极区域。 第一伪栅极被各向同性地蚀刻以形成比第一伪栅极薄的第二虚拟栅极。 注入第二离子以在未被第二伪栅极覆盖的每个有源区域中形成轻掺杂的源极/漏极区域。 电介质隔板形成在第二伪栅极的侧壁上，并且源极/漏极区域被硅化。 介电层沉积并平面化到第二虚拟栅极。 此后，去除第二伪栅极，在电介质层中留下栅极开口。 在PMOS有源区上形成掩模。 第一金属层沉积在NMOS有源区中的栅极开口中并且平坦化到掩模。 去除面具。 第二金属层沉积在PMOS有源区的栅极开口中。 将第一和第二金属层抛光到介电层，从而在集成电路的制造中完成双金属栅极CMOS晶体管的形成。