公开(公告)号：US06670237B1

公开(公告)日：2003-12-30

申请号：US10209729

申请日：2002-08-01

申请人： Wye Boon Loh ,  Chit Hwei Ng

发明人： Wye Boon Loh ,  Chit Hwei Ng

IPC分类号： H01L218242

CPC分类号： H01L28/40 ,  H01L21/76838 ,  H01L23/5223 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for forming a capacitor in a semiconductor device. An embodiment simultaneously forms a MIM capacitor and a dual damascene interconnect using common process steps. An embodiment comprises: forming a capacitor bottom plate and a first metal line over the semiconductor structure. We form a second dielectric layer over the capacitor bottom plate, the first metal line, and a first dielectric layer. Next, we form a top plate opening in the second dielectric layer to at least partially expose the capacitor bottom plate. A capacitor dielectric layer is formed over the capacitor bottom plate and the second dielectric layer. A capacitor top plate is formed in the top plate opening. Subsequently, we form a via opening through at least the second dielectric layer, the capacitor dielectric layer over the first metal line to expose a portion of the first metal line. Next, we fill the via opening with a second metal layer to form a via plug. A third dielectric layer is formed over the via plug and the capacitor top plate. We form a first trench opening and a second trench opening through the third dielectric layer, the second passivation layer and the third passivation layer. The first trench opening exposes a portion of the capacitor top plate. The second trench opening exposes a portion of the via plug. Next, we form a first trench plug in first trench opening and a second trench plug is the second trench opening. The top plate, the capacitor dielectric and the bottom plate form a capacitor.

摘要翻译： 一种在半导体器件中形成电容器的方法。 一个实施例同时使用常规的工艺步骤形成MIM电容器和双镶嵌互连。 一个实施例包括：在半导体结构上形成电容器底板和第一金属线。 我们在电容器底板，第一金属线和第一介电层之上形成第二电介质层。 接下来，我们在第二电介质层中形成顶板开口以至少部分地暴露电容器底板。 在电容器底板和第二电介质层上形成电容器电介质层。 在顶板开口中形成电容器顶板。 随后，我们通过至少第二电介质层，第一金属线上的电容器电介质层形成通孔，以露出第一金属线的一部分。 接下来，我们用通孔开口填充第二金属层以形成通孔塞。 在通孔插头和电容器顶板之上形成第三电介质层。 我们形成通过第三介电层，第二钝化层和第三钝化层的第一沟槽开口和第二沟槽开口。 第一沟槽开口露出电容器顶板的一部分。 第二沟槽开口暴露通孔塞的一部分。 接下来，我们在第一沟槽开口中形成第一沟槽塞，第二沟槽塞是第二沟槽开口。 顶板，电容器电介质和底板形成电容器。

公开(公告)号：US06468906B1

公开(公告)日：2002-10-22

申请号：US09617009

申请日：2000-07-14

申请人： Lap Chan ,  Kuan Pei Yap ,  Kheng Chok Tee ,  Flora S. Ip ,  Wye Boon Loh

发明人： Lap Chan ,  Kuan Pei Yap ,  Kheng Chok Tee ,  Flora S. Ip ,  Wye Boon Loh

IPC分类号： H01L2144

CPC分类号： H01L21/76849 ,  H01L21/76858 ,  H01L21/76867 ,  H01L21/76886

摘要： An interconnect line on an IMD layer on a semiconductor device is formed in an interconnect hole in the IMD layer. The interconnect hole has walls and a bottom in the IMD layer. A diffusion barrier is formed on the walls and the bottom of the hole. Fill the interconnect hole with a copper metal line. Perform a CMP step to planarize the device and to remove copper above the IMD layer. Deposit a passivating metal layer on the surface of the copper metal line encapsulating the copper metal line at the top of the hole. Alternatively, a blanket deposit of a copper metal line layer covers the diffusion layer and fills the interconnect hole with a copper metal line. Perform a CMP process to planarize the device to remove copper above the IMD layer. Deposit a passivating metal layer on the surface of the copper metal line encapsulating the copper metal line at the top of the hole in a self-aligned deposition process.

摘要翻译： 在IMD层中的互连孔中形成半导体器件上的IMD层上的互连线。 互连孔在IMD层中具有壁和底部。 在孔的壁和底部形成扩散阻挡层。 用铜金属线填充互连孔。 执行CMP步骤以使器件平坦化，并移除IMD层上方的铜。 在孔的顶部包埋铜金属线的铜金属线的表面上沉积钝化金属层。 或者，铜金属线层的覆盖沉积覆盖扩散层并用铜金属线填充互连孔。 执行CMP工艺以平坦化器件以去除IMD层上方的铜。 在自对准沉积工艺中，在孔的顶部封装铜金属线的铜金属线的表面上沉积钝化金属层。

公开(公告)号：US06492242B1

公开(公告)日：2002-12-10

申请号：US09609447

申请日：2000-07-03

申请人： Alex See ,  Cher Liang Randall Cha ,  Shyuz Fong Quek ,  Ting Cheong Ang ,  Wye Boon Loh ,  Sang Yee Loong ,  Jun Song ,  Chua Chee Tee

发明人： Alex See ,  Cher Liang Randall Cha ,  Shyuz Fong Quek ,  Ting Cheong Ang ,  Wye Boon Loh ,  Sang Yee Loong ,  Jun Song ,  Chua Chee Tee

IPC分类号： H01L2120

CPC分类号： H01L28/40 ,  H01L21/31683

摘要： A process for forming a high dielectric constant, (High K), layer, for a metal-oxide-metal, capacitor structure, featuring localized oxidation of an underlying metal layer, performed at a temperature higher than the temperature experienced by surrounding structures, has been developed. A first iteration of this process features the use of a laser ablation procedure, performed to a local region of an underlying metal layer, in an oxidizing ambient. The laser ablation procedure creates the desired, high temperature, only at the laser spot, allowing a high K layer to be created at this temperature, while the surrounding structures on a semiconductor substrate, not directly exposed to the laser ablation procedure remain at lower temperatures. A second iteration features the exposure of specific regions of an underlying metal layer, to a UV, or to an I line exposure procedure, performed in an oxidizing ambient, with the regions of an underlying metal layer exposed to the UV or I line procedure, via clear regions in an overlying photolithographic plate. This procedure also results in the formation of a high K layer, on a top portion of the underlying metal layer.

摘要翻译： 在高于周围结构所经历的温度的温度下进行的金属氧化物 - 金属电容器结构的高介电常数（高K）层，其特征在于底层金属层的局部氧化， 已经开发 该方法的第一次迭代的特征在于在氧化环境中使用对底层金属层的局部区域进行的激光烧蚀程序。 激光烧蚀过程仅在激光点产生所需的高温，允许在该温度下产生高K层，而不直接暴露于激光烧蚀过程的半导体衬底上的周围结构保持在较低温度 。 第二次迭代的特征在于在氧化环境中进行的底层金属层的特定区域到UV或I线曝光程序，暴露于UV或I线程序的下面的金属层的区域， 通过覆盖光刻板中的透明区域。 该过程还导致在下面的金属层的顶部上形成高K层。

公开(公告)号：US08645876B2

公开(公告)日：2014-02-04

申请号：US13234117

申请日：2011-09-15

申请人： Wye Boon Loh ,  Jeoung Mo Koo ,  Paul Kim Cheong Soh ,  Beng Lye Oh ,  Purakh Raj Verma

发明人： Wye Boon Loh ,  Jeoung Mo Koo ,  Paul Kim Cheong Soh ,  Beng Lye Oh ,  Purakh Raj Verma

IPC分类号： G06F17/50

CPC分类号： G06F17/5081

摘要： There is provided a method comprising receiving data corresponding to a layout design for a plurality of input mask layers and generating a layout design for at least one generated mask layer. The relationship between a first geometric element in a first layout pattern comprising one or more of the generated mask layers and a second geometric element in a second layout pattern is then determined and verified to check if they comply with predetermined rules. If the relationship does not conform with the predetermined rules the design of at least one of the generated mask layers associated with the first or second layout pattern is modified.

摘要翻译： 提供了一种方法，包括接收对应于多个输入掩模层的布局设计的数据，并且生成用于至少一个生成的掩模层的布局设计。 然后确定并验证包括生成的掩模层中的一个或多个的第一布局图案中的第一几何元素与第二布局图案中的第二几何元素之间的关系，以检查它们是否符合预定规则。 如果关系不符合预定规则，则修改与第一或第二布局图案相关联的所生成的掩模层中的至少一个的设计。

公开(公告)号：US06764914B2

公开(公告)日：2004-07-20

申请号：US10290130

申请日：2002-11-07

申请人： Alex See ,  Cher Liang Randall Cha ,  Shyue Fong Quek ,  Ting Cheong Ang ,  Wye Boon Loh ,  Sang Yee Loong ,  Jun Song ,  Chua Chee Tee

发明人： Alex See ,  Cher Liang Randall Cha ,  Shyue Fong Quek ,  Ting Cheong Ang ,  Wye Boon Loh ,  Sang Yee Loong ,  Jun Song ,  Chua Chee Tee

IPC分类号： H01L2120

CPC分类号： H01L28/40 ,  H01L21/31683

摘要： A process for forming a high dielectric constant, (High K), layer, for a metal-oxide-metal, capacitor structure, featuring localized oxidation of an underlying metal layer, performed at a temperature higher than the temperature experienced by surrounding structures, has been developed. A first iteration of this process features the use of a laser ablation procedure, performed to a local region of an underlying metal layer, in an oxidizing ambient. The laser ablation procedure creates the desired, high temperature, only at the laser spot, allowing a high K layer to be created at this temperature, while the surrounding structures on a semiconductor substrate, not directly exposed to the laser ablation procedure remain at lower temperatures. A second iteration features the exposure of specific regions of an underlying metal layer, to a UV, or to an I line exposure procedure, performed in an oxidizing ambient, with the regions of an underlying metal layer exposed to the UV or I line procedure, via clear regions in an overlying photolithographic plate. This procedure also results in the formation of a high K layer, on a top portion of the underlying metal layer.

摘要翻译： 在高于周围结构所经历的温度的温度下进行的金属氧化物 - 金属电容器结构的高介电常数（高K）层，其特征在于底层金属层的局部氧化， 已经开发 该方法的第一次迭代的特征在于在氧化环境中使用对底层金属层的局部区域进行的激光烧蚀程序。 激光烧蚀过程仅在激光点产生所需的高温，允许在该温度下产生高K层，而不直接暴露于激光烧蚀过程的半导体衬底上的周围结构保持在较低温度 。 第二次迭代的特征在于在氧化环境中进行的底层金属层的特定区域到UV或I线曝光程序，暴露于UV或I线程序的下面的金属层的区域， 通过覆盖光刻板中的透明区域。 该过程还导致在下面的金属层的顶部上形成高K层。

公开(公告)号：US6100195A

公开(公告)日：2000-08-08

申请号：US222275

申请日：1998-12-28

申请人： Lap Chan ,  Kuan Pei Yap ,  Kheng Chok Tee ,  Flora S. Ip ,  Wye Boon Loh

发明人： Lap Chan ,  Kuan Pei Yap ,  Kheng Chok Tee ,  Flora S. Ip ,  Wye Boon Loh

IPC分类号： H01L21/768 ,  H01L21/44

CPC分类号： H01L21/76849 ,  H01L21/76858 ,  H01L21/76867 ,  H01L21/76886

摘要： An interconnect line on an IMD layer on a semiconductor device is formed in an interconnect hole in the IMD layer. The interconnect hole has walls and a bottom in the IMD layer. A diffusion barrier is formed on the walls and the bottom of the hole. Fill the interconnect hole with a copper metal line. Perform a CMP step to planarize the device and to remove copper above the IMD layer. Deposit a passivating metal layer on the surface of the copper metal line encapsulating the copper metal line at the top of the hole. Alternatively, a blanket deposit of a copper metal line layer covers the diffusion layer and fills the interconnect hole with a copper metal line. Perform a CMP process to planarize the device to remove copper above the IMD layer. Deposit a passivating metal layer on the surface of the copper metal line encapsulating the copper metal line at the top of the hole in a self-aligned deposition process.

公开(公告)号：US06323125B1

公开(公告)日：2001-11-27

申请号：US09282065

申请日：1999-03-29

申请人： Choi Pheng Soo ,  Wye Boon Loh ,  Lap Chan

发明人： Choi Pheng Soo ,  Wye Boon Loh ,  Lap Chan

IPC分类号： H01L214763

CPC分类号： H01L21/76825 ,  H01L21/02164 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/3121 ,  H01L21/76808 ,  H01L2221/1031 ,  H01L2924/0002 ,  H01L2924/00

摘要： Only one photo mask defines the metal trench and via region. The mask blocks the UV light in the trench and via area forming Plasma Polymerized Methylsilane Oxide (PPMSO) in the exposed areas. Two step RIE plasma treatment using chlorine gas and oxygen gas removes the Plasma Polymerized Methylsilane (PPMS) in the trench and via regions. Conductive metal is deposited. A CMP process polishes back both excess metal along with the PPMSO, at a similar rate, to form: conducting metal lines, interconnects, and via contacts without metal dishing.

摘要翻译： 只有一个光罩定义了金属沟槽和通孔区域。 掩模在暴露的区域中阻挡沟槽中的UV光和形成等离子聚合甲基硅烷氧化物（PPMSO）的通孔区域。 使用氯气和氧气的两步RIE等离子体处理在沟槽和通孔区域中除去等离子体聚合甲基硅烷（PPMS）。 导电金属被沉积。 CMP工艺以类似的速率抛光多余金属与PPMSO，以形成：导电金属线，互连和通孔触点，而不会金属凹陷。