SUPPORTING FLOW CONTROL MECHANISM OF BUS BETWEEN SEMICONDUCTOR DIES ASSEMBLED IN WAFER-LEVEL PACKAGE
    21.
    发明申请
    SUPPORTING FLOW CONTROL MECHANISM OF BUS BETWEEN SEMICONDUCTOR DIES ASSEMBLED IN WAFER-LEVEL PACKAGE 审中-公开
    支持在水平包装中组装的半导体套管之间的总线的流量控制机制

    公开(公告)号:US20160239446A1

    公开(公告)日:2016-08-18

    申请号:US15043622

    申请日:2016-02-15

    Applicant: MEDIATEK INC.

    Inventor: Yao-Chun Su

    Abstract: A semiconductor die assembled in a wafer-level package includes a communication interface and a bus master. The bus master is coupled to a communication bus through the communication interface. The bus master communicates with a bus slave of another semiconductor die assembled in the wafer-level package via the communication bus, and is controlled by a flow control mechanism that manages a transaction flow initiated by the bus master over the communication bus.

    Abstract translation: 组装在晶片级封装中的半导体管芯包括通信接口和总线主设备。 总线主机通过通信接口耦合到通信总线。 总线主机经由通信总线与组装在晶片级封装中的另一个半导体管芯的总线从站进行通信,并由通过通信总线管理由总线主控器发起的事务流的流控制机构来控制。

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