公开(公告)号：US20230044797A1

公开(公告)日：2023-02-09

申请号：US17973318

申请日：2022-10-25

Applicant: MediaTek Inc.

Inventor： Yao-Chun Su ,  Chih-Ching Chen ,  I-Hsuan Peng ,  Yi-Jou Lin

IPC: H01L25/16 ,  H01L23/16 ,  H01L23/31 ,  H01L23/367 ,  H01L23/538 ,  H01L23/00 ,  H01L49/02

Abstract: A semiconductor package including at least one functional die; at least one dummy die free of active circuit, wherein the dummy die comprises at least one metal-insulator-metal (MIM) capacitor; and a redistribution layer (RDL) structure interconnecting the MIM capacitor to the at least one functional die.

公开(公告)号：US09846657B2

公开(公告)日：2017-12-19

申请号：US14934085

申请日：2015-11-05

Applicant: MEDIATEK INC.

Inventor： Chen-Hao Chang ,  Yao-Chun Su ,  Shin-Shiun Chen ,  Hong-Ching Chen

IPC: G06F13/10 ,  G06F13/22 ,  G06F13/40 ,  G06F13/42

CPC classification number: G06F13/102 ,  G06F13/22 ,  G06F13/4068 ,  G06F13/4282

Abstract: An electronic device includes a control circuit and a bus interface. The control circuit packs a plurality of commands in a compound command frame. The bus interface communicates with another electronic device via a bus between the electronic device and the another electronic device, and packs the compound command frame in a single packet and transmits the single packet over the bus.

公开(公告)号：US20160232111A1

公开(公告)日：2016-08-11

申请号：US14934085

申请日：2015-11-05

Applicant: MEDIATEK INC.

Inventor： Chen-Hao Chang ,  Yao-Chun Su ,  Shin-Shiun Chen ,  Hong-Ching Chen

IPC: G06F13/10 ,  G06F9/30 ,  G06F13/42 ,  G06F13/22 ,  G06F13/40

CPC classification number: G06F13/102 ,  G06F13/22 ,  G06F13/4068 ,  G06F13/4282

Abstract: An electronic device includes a control circuit and a bus interface. The control circuit packs a plurality of commands in a compound command frame. The bus interface communicates with another electronic device via a bus between the electronic device and the another electronic device, and packs the compound command frame in a single packet and transmits the single packet over the bus.

Abstract translation: 电子设备包括控制电路和总线接口。 控制电路在复合命令帧中封装多个命令。 总线接口通过电子设备和另一电子设备之间的总线与另一电子设备通信，并将复合命令帧打包在单个分组中，并通过总线发送单个分组。

公开(公告)号：US20150339253A1

公开(公告)日：2015-11-26

申请号：US14583206

申请日：2014-12-26

Applicant: MEDIATEK INC.

Inventor： Shin-Shiun Chen ,  Chen-Hao Chang ,  Hong-Ching Chen ,  Yao-Chun Su

IPC: G06F13/42 ,  G06F13/364

CPC classification number: G06F13/4221 ,  G06F13/364

Abstract: An electronic device has a management data input/output (MDIO) bus, a control unit, and an MDIO master. The control circuit receives a host command from a host device, and outputs a plurality of MDIO commands in response to the host command. The MDIO master receives the MDIO commands from the control circuit, and transmits the MDIO commands to the MDIO bus.

Abstract translation: 电子设备具有管理数据输入/输出（MDIO）总线，控制单元和MDIO主机。 控制电路从主机装置接收主机命令，并响应主机命令输出多个MDIO命令。 MDIO主机从控制电路接收MDIO命令，并将MDIO命令发送到MDIO总线。

公开(公告)号：US12183723B2

公开(公告)日：2024-12-31

申请号：US17973318

申请日：2022-10-25

Applicant: MediaTek Inc.

Inventor： Yao-Chun Su ,  Chih-Ching Chen ,  I-Hsuan Peng ,  Yi-Jou Lin

IPC: H01L25/16 ,  H01L23/00 ,  H01L23/16 ,  H01L23/31 ,  H01L23/367 ,  H01L23/538 ,  H01L49/02

Abstract: A semiconductor package including at least one functional die; at least one dummy die free of active circuit, wherein the dummy die comprises at least one metal-insulator-metal (MIM) capacitor; and a redistribution layer (RDL) structure interconnecting the MIM capacitor to the at least one functional die.

公开(公告)号：US10152445B2

公开(公告)日：2018-12-11

申请号：US15009819

申请日：2016-01-28

Applicant: MEDIATEK INC.

Inventor： Yao-Chun Su

IPC: G06F13/00 ,  G06F13/38 ,  G06F13/40 ,  G06F13/42 ,  G06F13/362 ,  G06F13/364 ,  H01L23/00

Abstract: A semiconductor die assembled in a wafer-level package includes a processing circuit, a multiplexer, and a transmit interface. The processing circuit generates a plurality of signal outputs. The multiplexer multiplexes the signal outputs into a multiplexed signal. The transmit interface transmits the multiplexed signal to another semiconductor die assembled in the wafer-level package.

公开(公告)号：US20240242016A1

公开(公告)日：2024-07-18

申请号：US18395633

申请日：2023-12-25

Applicant: MEDIATEK INC.

Inventor： Chih-Jung Hsu ,  Chen Lien ,  Deng-Yao Tu ,  Po-Yang Chen ,  Guan-Qi Fang ,  Shu-Huan Chang ,  Yi-Hung Chen ,  Yao-Chun Su ,  Yu-Yang Chen

IPC: G06F30/394 ,  G06F30/392 ,  G06F119/02

CPC classification number: G06F30/394 ,  G06F30/392 ,  G06F2119/02

Abstract: A layout routing method includes determining a routing pattern according to a swapping rule, a via pattern, area constraints and pin locations; optimizing swapping in differential pairs according to the routing pattern; extracting features of each routing net to obtain extracted features; using an unsupervised algorithm to generate different routing groups according to the extracted features; and determining a routing order of the routing groups according to complex features of the routing groups.

公开(公告)号：US11222850B2

公开(公告)日：2022-01-11

申请号：US16846381

申请日：2020-04-12

Applicant: MEDIATEK INC.

Inventor： Yao-Chun Su ,  Chih-Jung Hsu ,  Yi-Jou Lin ,  I-Hsuan Peng

IPC: H01L23/538 ,  H01L23/31 ,  H01L23/367 ,  H01L23/00 ,  H01L23/58 ,  H01L23/66 ,  H01L25/065

Abstract: An electronic package configured to operate at Gigabit-per-second (Gbps) data rates is disclosed. The electronic package includes a package substrate of a rectangular shape. A chip package having a first high-speed interface circuit die is mounted on a top surface of the package substrate. The chip package is rotated relative to the package substrate above a vertical axis that is orthogonal to the top surface through about 45 degrees. The first high-speed interface circuit die includes a first Serializer/Deserializer (SerDes) circuit block.

公开(公告)号：US09934179B2

公开(公告)日：2018-04-03

申请号：US15043611

申请日：2016-02-14

Applicant: MEDIATEK INC.

Inventor： Yao-Chun Su

IPC: H01L21/44 ,  G06F13/368 ,  G06F13/40 ,  H01L23/498 ,  H01L25/065

CPC classification number: G06F13/368 ,  G06F13/4068 ,  H01L23/49811 ,  H01L23/49838 ,  H01L25/065 ,  H01L2225/06506 ,  H01L2225/06527

Abstract: A wafer-level package has a first input/output (I/O) port, a second I/O port, a first semiconductor die, and a second semiconductor die. The first I/O port and the second I/O port of the wafer-level package are arranged to connect at least one management bus. The first semiconductor die and the second semiconductor die assembled in the wafer-level package are arranged to receive commands from the first I/O port and the second I/O port, respectively.

公开(公告)号：US20170147517A1

公开(公告)日：2017-05-25

申请号：US15221589

申请日：2016-07-27

Applicant: MEDIATEK INC.

Inventor： Shin-Shiun Chen ,  Yi-Wen Chien ,  Yao-Chun Su ,  Chih-Kang Lin

IPC: G06F13/28 ,  G06F13/16 ,  G06F13/42 ,  G06F13/40

CPC classification number: G06F13/28 ,  G06F13/1673 ,  G06F13/4022 ,  G06F13/4282

Abstract: A direct memory access (DMA) system is implemented in an electronic device that communicates with a host device via a communication bus, and includes an available descriptor notification circuit and a DMA controller. The available descriptor notification circuit indicates whether at least one valid descriptor is available in the host device. The available descriptor notification circuit is set by at least the host device. The at least one valid descriptor records DMA data transfer control information. The DMA controller fetches the at least one valid descriptor from the host device when the available descriptor notification circuit indicates that the at least one valid descriptor is available in the host device, and refers to the at least one valid descriptor fetched from the host device to perform a DMA data transfer between the electronic device and the host device.