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公开(公告)号：US20240324194A1
公开(公告)日：2024-09-26
申请号：US18602778
申请日：2024-03-12
发明人： Dongjin LEE , Junhee LIM , Hakseon KIM , Kangoh YUN , Sohyun LEE
CPC分类号： H10B41/35 , G11C16/0483 , H01L25/0652 , H10B41/10 , H10B41/27 , H10B41/41 , H10B80/00 , H01L2225/06506
摘要： An integrated circuit device includes a substrate including an active region including a central active region, base active regions and extended active regions integrated together and defined by a device isolation film. A drain region is located in the central active region, and source regions are respectively located in the base active regions. The base active regions are spaced apart from each other in different diagonal directions with respect to the central active region in a plan view. The extended active regions each have an L-shape, connect the central active region and the base active regions, and are spaced apart from each other. Gate structures that respectively cross the base active regions and are spaced apart from each other on the substrate. The central active region, the extended active regions, the base active regions, and the gate structures configure pass transistors, and the pass transistors share the drain region.
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2.发明公开公开(公告)号：US20240321774A1
公开(公告)日：2024-09-26
申请号：US18399519
申请日：2023-12-28
发明人： Kitae Park , Chiwan Song , Seonkyu Kim , Hyunna Bae , Seungmin Baek , Yongjae Song , Joonseok Oh , Jaewook Jung , Seokil Hong
IPC分类号： H01L23/00 , H01L21/02 , H01L21/3205 , H01L23/31 , H01L23/492 , H01L25/065 , H10B80/00
CPC分类号： H01L23/562 , H01L21/0214 , H01L21/02249 , H01L21/02252 , H01L21/32055 , H01L23/3135 , H01L23/4926 , H01L24/48 , H01L25/0657 , H10B80/00 , H01L2224/48149 , H01L2224/48227 , H01L2225/06506 , H01L2225/0651 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06562 , H01L2924/3511 , H01L2924/3512
摘要： The present disclosure relates to semiconductor devices and semiconductor packages. One example semiconductor device includes a crystalline silicon layer, an amorphous silicon layer on the crystalline silicon layer and extending along a first surface of the crystalline silicon layer, and a dielectric layer on the amorphous silicon layer and extending along a surface of the amorphous silicon layer. The dielectric layer includes silicon oxynitride and has compressive stress.
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公开(公告)号：US20240321622A1
公开(公告)日：2024-09-26
申请号：US18474455
申请日：2023-09-26
发明人： YOUNG-JA KIM
IPC分类号： H01L21/683 , H01L21/60
CPC分类号： H01L21/6838 , H01L21/60 , H01L24/16 , H01L24/32 , H01L24/73 , H01L25/0657 , H01L2224/16227 , H01L2224/32225 , H01L2224/73204 , H01L2225/06506 , H01L2225/0651 , H01L2225/06562
摘要： An adsorption device for a reflow process according to an embodiment is coupled to a semiconductor package to form a reflow assembly in a reflow process. The semiconductor package includes a substrate and a semiconductor chip disposed at one surface of the substrate. The adsorption device for the reflow process includes a main body and a pressure control member. The main body includes an inner space portion and includes a bottom portion and a substrate adsorption portion that protrudes from the bottom portion to be adhered to the one surface of the substrate in an outer region of the semiconductor chip by a negative pressure. The pressure control member maintains a pressure of the inner space portion.
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4.发明公开公开(公告)号：US20240315039A1
公开(公告)日：2024-09-19
申请号：US18483331
申请日：2023-10-09
发明人： Gyeongsik EOM , Inho KIM , Chankyu KIM , Jumi YUN , Young-Ho LEE , Dasom JUNG , Wongi HONG
IPC分类号： H10B43/40 , H01L25/065 , H10B41/10 , H10B41/27 , H10B41/35 , H10B41/40 , H10B43/10 , H10B43/27 , H10B43/35 , H10B80/00
CPC分类号： H10B43/40 , H01L25/0652 , H10B41/10 , H10B41/27 , H10B41/35 , H10B41/40 , H10B43/10 , H10B43/27 , H10B43/35 , H10B80/00 , H01L2225/06506
摘要： A semiconductor device includes a cell area, wherein the cell area includes: a cell array area; a connection area; a gate stacking structure including a plurality of gate electrodes, wherein the gate stacking structure includes an upper structure and a lower structure; a plurality of channel structures that penetrates the gate stacking structure in the cell array area; and a plurality of gate contact portions that penetrates the gate stacking structure in the connection area, wherein a bottom gate electrode in the cell array area is in a bottom portion of the upper structure and is adjacent to a channel structure among the plurality of channel structures, and wherein a bottom insulating portion in the connection area is in the bottom portion of the upper structure and is adjacent to a gate contact portion among the plurality of gate contact portions.
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公开(公告)号：US20240314929A1
公开(公告)日：2024-09-19
申请号：US18588633
申请日：2024-02-27
申请人： Kioxia Corporation
发明人： Kiyokazu ISHIZAKI
IPC分类号： H05K1/11 , H01L23/31 , H01L23/498 , H01L25/065 , H05K1/18
CPC分类号： H05K1/117 , H01L23/3128 , H01L23/49816 , H01L25/0652 , H05K1/111 , H05K1/181 , H01L2225/06506 , H01L2225/06562 , H01L2225/06586 , H05K2201/0939 , H05K2201/09409 , H05K2201/10734 , H05K2201/10984
摘要： A semiconductor storage device includes a wiring pattern on an insulating base material; an insulating film covering partially the wiring pattern; and an electronic component. The wiring pattern includes a first pad having an edge in an arc shape, and a first wire. The insulating film has a first opening larger than the first pad. The first wire has a first portion, a second portion, and a third portion. The first portion is connected to the first pad inside the first opening extends in a first direction. The second portion is connected to the first pad inside the first opening and extends in a second direction. The third portion is connected to the first portion and the second portion. The first wire is connected with the first pad in an angular range of not more than 90 degrees in a circumferential direction of the first pad.
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公开(公告)号：US20240312916A1
公开(公告)日：2024-09-19
申请号：US18361168
申请日：2023-07-28
IPC分类号： H01L23/538 , H01L23/00 , H01L23/498 , H01L25/065
CPC分类号： H01L23/5384 , H01L23/49816 , H01L24/48 , H01L25/0657 , H01L2224/48106 , H01L2224/48145 , H01L2224/48157 , H01L2224/48227 , H01L2225/06506 , H01L2225/0651 , H01L2225/06537 , H01L2225/06562 , H01L2924/1438
摘要： A semiconductor device package includes a substrate, a stack of memory dies positioned on the substrate, and an interposer spaced from the stack of memory dies and also positioned on the substrate. First and second sets of bond pads are electrically connected to the substrate, where the second set of bond pads is positioned on the interposer above the substrate. A first set of bond wires electrically connects a first sub-stack of the memory dies to the first set of bond pads. A second set of bond wires electrically connects a second sub-stack of memory dies, positioned above the first sub-stack, to the second set of bond wires. The first and second sub-stacks of memory dies may be electrically isolated from one another to reduce noise in electrical signals transmitted to and from the memory dies.
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公开(公告)号：US12083715B2
公开(公告)日：2024-09-10
申请号：US17540371
申请日：2021-12-02
发明人： Xianlu Cui , Junrong Yan , C K Chin , Tao Shi
IPC分类号： B29C43/58 , B29C41/18 , B29C43/18 , G05B19/4097 , H01L21/56 , B29K63/00 , B29L31/34 , H01L25/065 , H01L25/18
CPC分类号： B29C43/58 , B29C43/18 , G05B19/4097 , H01L21/561 , B29C2043/182 , B29C2043/5825 , B29K2063/00 , B29L2031/34 , G05B2219/45031 , H01L25/0657 , H01L25/18 , H01L2225/06506 , H01L2225/0651 , H01L2225/06562 , H01L2225/06586
摘要： A molding compound dispensing system identifies a semiconductor device strip having a substrate with a plurality of segments allocated for die stacks. The system obtains topological data of the identified semiconductor device strip for each of the segments, including data indicative of any semiconductor components in each respective segment. The system determines an amount of molding compound to be applied to each of the segments based on the topological data for each respective segment, and causes a molding compound dispenser to dispense the determined amounts of molding compound at each of the segments.
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8.发明公开公开(公告)号：US20240282753A1
公开(公告)日：2024-08-22
申请号：US18634014
申请日：2024-04-12
发明人： Eunji KIM , Seungwoo PAEK , Byungkyu KIM , Sangjun PARK , Sungdong CHO
IPC分类号： H01L25/065 , H01L23/00 , H01L23/498 , H01L23/522 , H01L23/528 , H01L23/532 , H01L23/538 , H01L29/423 , H10B43/27 , H10B43/35 , H10B43/40
CPC分类号： H01L25/0657 , H01L23/49816 , H01L23/49822 , H01L23/49838 , H01L23/5226 , H01L23/5283 , H01L23/53209 , H01L23/5383 , H01L23/5386 , H01L24/08 , H01L29/42344 , H10B43/40 , H01L2224/08146 , H01L2225/06506 , H01L2225/0651 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06562 , H01L2924/1431 , H01L2924/1438 , H10B43/27 , H10B43/35
摘要： A device including a first structure and a second structure is provided. The device includes a substrate, a peripheral circuit and first junction pads on the substrate; a first insulating structure surrounding side surfaces of the first junction pads; second junction pads contacting the first junction pads; a second insulating structure on the first insulating structure; a passivation layer on the second insulating structure; an upper insulating structure between the passivation layer and the second insulating structure; a barrier capping layer between the upper insulating structure and the passivation layer; conductive patterns spaced apart from each other in the upper insulating structure; a first pattern structure between the upper insulating structure and the second insulating structure; a stack structure between the second insulating structure and the first pattern structure, and including gate layers; and a vertical structure passing through the stack structure and including a data storage structure and a channel layer.
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公开(公告)号：US20240282684A1
公开(公告)日：2024-08-22
申请号：US18641480
申请日：2024-04-22
申请人： RESONAC CORPORATION
IPC分类号： H01L23/498 , H01L21/48 , H01L23/12 , H01L23/14 , H01L23/32 , H01L23/538 , H01L25/065 , H05K1/09
CPC分类号： H01L23/49822 , H01L21/4857 , H01L23/12 , H01L23/145 , H01L23/32 , H01L23/49866 , H01L23/49894 , H01L23/5383 , H01L23/5384 , H01L23/5386 , H01L23/5389 , H01L25/0652 , H01L2225/06506 , H01L2225/06548 , H01L2225/06572 , H05K1/09
摘要： An organic interposer includes: a first organic insulating layer including a groove; a first metal wire located in the groove; a barrier metal material covering the first metal wire; and a second metal wire located above the first metal wire, wherein the barrier metal material includes: a first barrier metal film interposed between the first metal wire and an inner surface of the groove; and a second barrier metal film located on the first metal wire, and wherein the second metal wire is in contact with both of the first barrier metal film and the second barrier metal film.
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公开(公告)号：US20240282385A1
公开(公告)日：2024-08-22
申请号：US18442943
申请日：2024-02-15
发明人： Mohammed A. Khan , Michael Wagner
IPC分类号： G11C16/20 , H01L25/065 , H01L25/18 , H10B80/00
CPC分类号： G11C16/20 , H01L25/0657 , H01L25/18 , H10B80/00 , H01L2225/06506 , H01L2225/06562
摘要： A method includes dividing an on-die capacitor of a memory device into a plurality of capacitor banks, charging the plurality of capacitor banks sequentially during an initialization of the memory device, determining a supply voltage for the memory device is below a threshold voltage, and discharging the plurality of capacitor banks sequentially to provide power to the memory device in response to determining the supply voltage is below the threshold voltage.
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