公开(公告)号：US20210201970A1

公开(公告)日：2021-07-01

申请号：US17200233

申请日：2021-03-12

Applicant: Micron Technology, Inc.

Inventor： Gary Howe ,  Eric J. Stave ,  Thomas H. Kinsley ,  Matthew A. Prather

IPC: G11C7/22 ,  G11C7/10 ,  G06F13/40 ,  G11C8/10

Abstract: Methods, systems, and apparatuses related to memory operation with on-die termination (ODT) are provided. A memory device may be configured to provide ODT at a first portion (e.g., rank) during multiple communications at a second portion (e.g., rank). For example, a memory device may receive a first command instructing a first portion to perform a first communication and instructing a second portion to enter an ODT mode. The device may perform, with the first portion, the first communication with a host while the second portion is in the ODT mode. The device may receive a second command instructing the first portion to perform a second communication, and the device may perform, with the first portion, the second communication while the second portion remains in the ODT mode. The second portion may persist in the ODT mode for an indicated number of communications, or until instructed to exit the ODT mode.

公开(公告)号：US10672496B2

公开(公告)日：2020-06-02

申请号：US15792473

申请日：2017-10-24

Applicant: Micron Technology, Inc.

Inventor： Joshua E. Alzheimer ,  Gary Howe ,  Harish N. Venkata

IPC: G11C29/00 ,  G11C29/10 ,  G11C29/02 ,  G11C29/12 ,  G11C29/16 ,  G11C29/46 ,  G11C29/20

Abstract: A memory device may include a command controller and a memory array with multiple memory cells. The command controller may receive commands to write a data pattern to the memory cells of the memory array. The data pattern may be repeated across multiple cells of the memory array without further input from input/output data lines. Additionally, the memory device may include one or more counters to assist in accessing the memory cells of the memory array.

公开(公告)号：US10664173B2

公开(公告)日：2020-05-26

申请号：US15883956

申请日：2018-01-30

Applicant: Micron Technology, Inc.

Inventor： Gary Howe ,  Liang Chen ,  Daniel B. Penney

IPC: G11B5/00 ,  G06F3/06

Abstract: Techniques provided herein compensate for an internal and external timing skew between a data strobe (DQS) and a clock (CLK), by: executing at least one write leveling initialization procedure (WLInit) that uses a mode-register-write (MRW) command to synchronize a timing between a data strobe (DQS) with a clock (CLK) based upon capture of an internal write command. Internal and external timing skew is identified based upon the WLInit. The internal timing skew is skew caused internal to a memory device and the external timing skew is skew caused external to the memory device. A timing between the DQS and the CLK is adjusted based upon the internal and external timing skew.

公开(公告)号：US20190122744A1

公开(公告)日：2019-04-25

申请号：US15792473

申请日：2017-10-24

Applicant: Micron Technology, Inc.

Inventor： Joshua E. Alzheimer ,  Gary Howe ,  Harish N. Venkata

IPC: G11C29/10

Abstract: A memory device may include a command controller and a memory array with multiple memory cells. The command controller may receive commands to write a data pattern to the memory cells of the memory array. The data pattern may be repeated across multiple cells of the memory array without further input from input/output data lines.

公开(公告)号：US10120647B2

公开(公告)日：2018-11-06

申请号：US15690085

申请日：2017-08-29

Applicant: Micron Technology, Inc.

Inventor： Brian Huber ,  Gary Howe

IPC: G06F5/06 ,  H03K5/26

Abstract: Apparatuses and methods for a timing domain transfer circuit are disclosed. Disclosed embodiments may be configured to receive an event from one timing domain, output the event to another timing domain, and further configured to mark the event as transferred. An example method includes receiving an Event in based in a first timing domain at a first latch and receiving an intermediate event from the first latch by a second latch. The event is transferred to a second timing domain by the second latch and the first latch is reset based on feedback.