公开(公告)号：US10482931B1

公开(公告)日：2019-11-19

申请号：US16137175

申请日：2018-09-20

Applicant: Micron Technology, Inc.

Inventor： Shinichi Miyatake

IPC: G11C7/00 ,  G11C7/06 ,  G11C11/4091 ,  G11C11/4096 ,  G11C11/4094

Abstract: Memory devices may employ flip-flops with paired transistors in sense amplifying circuitry to sense charges stored in memory cells. Paired transistors may present mismatches in electrical characteristics, which may affect the sensitivity of the sense amplifying circuitry. Embodiments include systems and methods that compensate and/or mitigate mismatches in the electrical characteristics of the paired transistors. To that end, the memory devices may sense the mismatches during a compensation period and pre-compensate the read-out of data lines to improve the sensibility of the sense amplifying circuitry.

公开(公告)号：US10236040B2

公开(公告)日：2019-03-19

申请号：US15351586

申请日：2016-11-15

Applicant: Micron Technology, Inc.

Inventor： Shinichi Miyatake

IPC: G11C7/12 ,  G11C11/4091 ,  G11C11/4094 ,  G11C7/10

Abstract: Apparatus and methods are disclosed, including an apparatus having a first transistor configured to be coupled to a first bit line, and a control circuit configured to supply a gate of the first transistor with a first voltage to turn on the first transistor, and to supply the gate of the first transistor with a second voltage higher than the first voltage to strengthen a current drive capability of the first transistor.

公开(公告)号：US10163906B2

公开(公告)日：2018-12-25

申请号：US15293554

申请日：2016-10-14

Applicant: Micron Technology, Inc.

Inventor： Shinichi Miyatake

IPC: H01L27/108 ,  G11C11/4091 ,  H01L27/112 ,  G11C11/4076 ,  G11C5/02 ,  G11C7/08 ,  G11C11/4074 ,  G11C11/4094 ,  G11C11/4097

Abstract: Some embodiments include apparatus and methods using a first diffusion region, a second diffusion region, a third diffusion region, and a fourth diffusion region; a first channel region located between a portion of the first diffusion region and a portion of the third diffusion region; a second channel region located between the portion of the third diffusion region and a portion of the second diffusion region; a third channel region located between the portion of the second diffusion region and a portion of the fourth diffusion region; and a gate located over the first, second, and third channel regions. The first and second diffusion regions are located on a first side of the gate. The third and fourth diffusion regions are located on a second side of the gate opposite from the first side.

公开(公告)号：US10665311B2

公开(公告)日：2020-05-26

申请号：US16357666

申请日：2019-03-19

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Shinichi Miyatake

IPC: G11C17/16 ,  G11C17/18 ,  G11C11/4074 ,  H01L23/525 ,  G11C29/00 ,  G11C29/02 ,  G11C11/401

Abstract: Apparatuses and methods including anti-fuses and for reading and programming same are disclosed herein. An example apparatus may include an anti-fuse element comprising first, second, and third transistors coupled in series between first and second nodes such that the second transistor is between the first and third transistors. The second transistor is configured to be operated such that a punch-through current flows through the second transistor to indicate that the anti-fuse element has been programmed.

公开(公告)号：US20190214103A1

公开(公告)日：2019-07-11

申请号：US16357666

申请日：2019-03-19

Applicant: Micron Technology, Inc.

Inventor： Shinichi Miyatake

IPC: G11C17/16 ,  G11C17/18 ,  H01L23/525 ,  G11C11/4074 ,  G11C29/00 ,  G11C29/02

CPC classification number: G11C17/16 ,  G11C11/401 ,  G11C11/4074 ,  G11C17/165 ,  G11C17/18 ,  G11C29/027 ,  G11C29/785 ,  G11C29/787 ,  H01L23/5252

Abstract: Apparatuses and methods including anti-fuses and for reading and programming same are disclosed herein. An example apparatus may include an anti-fuse element comprising first, second, and third transistors coupled in series between first and second nodes such that the second transistor is between the first and third transistors. The second transistor is configured to be operated such that a punch-through current flows through the second transistor to indicate that the anti-fuse element has been programmed.

公开(公告)号：US20190172508A1

公开(公告)日：2019-06-06

申请号：US16269886

申请日：2019-02-07

Applicant: Micron Technology, Inc.

Inventor： Shinichi Miyatake

IPC: G11C7/12 ,  G11C11/4094 ,  G11C11/4091

CPC classification number: G11C7/12 ,  G11C7/1048 ,  G11C11/4091 ,  G11C11/4094

Abstract: Apparatus and methods are disclosed, including an apparatus having a first transistor configured to be coupled to a first bit line, and a control circuit configured to supply a gate of the first transistor with a first voltage to turn on the first transistor, and to supply the gate of the first transistor with a second voltage higher than the first voltage to strengthen a current drive capability of the first transistor.

公开(公告)号：US20190088654A1

公开(公告)日：2019-03-21

申请号：US16197185

申请日：2018-11-20

Applicant: Micron Technology, Inc.

Inventor： Shinichi Miyatake

IPC: H01L27/108 ,  G11C11/4091 ,  G11C11/4076 ,  H01L27/112 ,  G11C11/4097 ,  G11C7/08 ,  G11C11/4074 ,  G11C11/4094 ,  G11C5/02

CPC classification number: H01L27/108 ,  G11C5/025 ,  G11C7/08 ,  G11C11/4074 ,  G11C11/4076 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4097 ,  H01L27/11286

Abstract: Some embodiments include apparatus and methods using a first diffusion region, a second diffusion region, a third diffusion region, and a fourth diffusion region; a first channel region located between a portion of the first diffusion region and a portion of the third diffusion region; a second channel region located between the portion of the third diffusion region and a portion of the second diffusion region; a third channel region located between the portion of the second diffusion region and a portion of the fourth diffusion region; and a gate located over the first, second, and third channel regions. The first and second diffusion regions are located on a first side of the gate. The third and fourth diffusion regions are located on a second side of the gate opposite from the first side.

公开(公告)号：US20180108398A1

公开(公告)日：2018-04-19

申请号：US15293554

申请日：2016-10-14

Applicant: Micron Technology, Inc.

Inventor： Shinichi Miyatake

IPC: G11C11/4091 ,  H01L27/112 ,  G11C11/4076 ,  G11C11/4096

CPC classification number: H01L27/108 ,  G11C5/025 ,  G11C7/08 ,  G11C11/4074 ,  G11C11/4076 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4097 ,  H01L27/11286

Abstract: Some embodiments include apparatus and methods using a first diffusion region, a second diffusion region, a third diffusion region, and a fourth diffusion region; a first channel region located between a portion of the first diffusion region and a portion of the third diffusion region; a second channel region located between the portion of the third diffusion region and a portion of the second diffusion region; a third channel region located between the portion of the second diffusion region and a portion of the fourth diffusion region; and a gate located over the first, second, and third channel regions. The first and second diffusion regions are located on a first side of the gate. The third and fourth diffusion regions are located on a second side of the gate opposite from the first side.