公开(公告)号：US08229907B2

公开(公告)日：2012-07-24

申请号：US12495582

申请日：2009-06-30

申请人： Jan Gray ,  Martin Taillefer ,  Yosseff Levanoni ,  Ali-Reza Adl-Tabatabai ,  Dave Detlefs ,  Michael Magruder ,  David Callahan

发明人： Jan Gray ,  Martin Taillefer ,  Yosseff Levanoni ,  Ali-Reza Adl-Tabatabai ,  Dave Detlefs ,  Michael Magruder ,  David Callahan

IPC分类号： G06F7/00

CPC分类号： G06F17/30377

摘要： Hardware assisted transactional memory system with open nested transactions. Embodiments include a system whereby hardware acceleration of transactions can be accomplished by implementing open nested transaction in hardware which respect software locks such that a top level transaction can be implemented in software, and thus not be limited by hardware constraints typical when using hardware transactional memory systems.

摘要翻译： 具有开放嵌套交易的硬件辅助事务内存系统。 实施例包括一种系统，其中可以通过在硬件中实现开放式嵌套事务来实现事务的硬件加速，这些交易涉及软件锁定，使得顶级事务可以以软件实现，因此不受硬件事务存储器系统典型的硬件约束的限制 。

公开(公告)号：US20100332538A1

公开(公告)日：2010-12-30

申请号：US12495582

申请日：2009-06-30

申请人： Jan Gray ,  Martin Taillefer ,  Yosseff Levanoni ,  Ali-Reza Adl-Tabatabai ,  Dave Detlefs ,  Michael Magruder ,  David Callahan

发明人： Jan Gray ,  Martin Taillefer ,  Yosseff Levanoni ,  Ali-Reza Adl-Tabatabai ,  Dave Detlefs ,  Michael Magruder ,  David Callahan

IPC分类号： G06F17/30

CPC分类号： G06F17/30377

摘要： Hardware assisted transactional memory system with open nested transactions. Some embodiments described herein implement a system whereby hardware acceleration of transactions can be accomplished by implementing open nested transaction in hardware which respect software locks such that a top level transaction can be implemented in software, and thus not be limited by hardware constraints typical when using hardware transactional memory systems.

摘要翻译： 具有开放嵌套交易的硬件辅助事务内存系统。 这里描述的一些实施例实现了一种系统，其中可以通过在硬件中实现开放式嵌套事务来实现事务的硬件加速，这些交易涉及软件锁定，使得顶级事务可以以软件实现，并且因此不受硬件约束的限制 事务性存储系统。

公开(公告)号：US08176253B2

公开(公告)日：2012-05-08

申请号：US11823236

申请日：2007-06-27

申请人： Martin Taillefer ,  Darek Mihocka ,  Bruno Silva

发明人： Martin Taillefer ,  Darek Mihocka ,  Bruno Silva

IPC分类号： G06F12/00 ,  G06F9/455 ,  G06F9/44

CPC分类号： G06F9/466 ,  G06F9/45504 ,  G06F9/45533 ,  G06F2209/521

摘要： Various technologies and techniques are disclosed for using transactional memory hardware to accelerate virtualization or emulation. A central processing unit is provided with the transactional memory hardware. Code backpatching can be facilitated by providing transactional memory hardware that supports a facility to maintain private memory state and an atomic commit feature. Changes made to certain code are stored in the private state facility. Backpatching changes are enacted by attempting to commit all the changes to memory at once using the atomic commit feature. An efficient call return stack can be provided by using transactional memory hardware. A call return cache stored in the private state facility captures a host address to return to after execution of a guest function completes. A direct-lookup hardware-based hash table is used for the call return cache.

摘要翻译： 公开了用于使用事务性存储器硬件来加速虚拟化或仿真的各种技术和技术。 中央处理单元设置有事务存储器硬件。 可以通过提供事务性存储器硬件来支持代码反向补丁，该硬件支持维护私有内存状态和原子提交功能的功能。 对某些代码所做的更改存储在私人状态设施中。 通过尝试使用原子提交功能一次性向内存提交所有更改来实现后期更改。 可以通过使用事务性存储器硬件来提供高效的回叫栈。 存储在私有状态设施中的调用返回缓存捕获主机地址以在执行客户机功能完成后返回。 直接查找基于硬件的哈希表用于调用返回缓存。

公开(公告)号：US20090006751A1

公开(公告)日：2009-01-01

申请号：US11823236

申请日：2007-06-27

申请人： Martin Taillefer ,  Darek Mihocka ,  Bruno Silva

发明人： Martin Taillefer ,  Darek Mihocka ,  Bruno Silva

IPC分类号： G06F12/00

CPC分类号： G06F9/466 ,  G06F9/45504 ,  G06F9/45533 ,  G06F2209/521

摘要： Various technologies and techniques are disclosed for using transactional memory hardware to accelerate virtualization or emulation. A central processing unit is provided with the transactional memory hardware. Code backpatching can be facilitated by providing transactional memory hardware that supports a facility to maintain private memory state and an atomic commit feature. Changes made to certain code are stored in the private state facility. Backpatching changes are enacted by attempting to commit all the changes to memory at once using the atomic commit feature. An efficient call return stack can be provided by using transactional memory hardware. A call return cache stored in the private state facility captures a host address to return to after execution of a guest function completes. A direct-lookup hardware-based hash table is used for the call return cache.

摘要翻译： 公开了用于使用事务性存储器硬件来加速虚拟化或仿真的各种技术和技术。 中央处理单元设置有事务存储器硬件。 可以通过提供事务性存储器硬件来支持代码反向补丁，该硬件支持维护私有内存状态和原子提交功能的功能。 对某些代码所做的更改存储在私人状态设施中。 通过尝试使用原子提交功能一次性向内存提交所有更改来实现后期更改。 可以通过使用事务性存储器硬件来提供高效的回叫栈。 存储在私有状态设施中的调用返回缓存捕获主机地址以在执行客户机功能完成后返回。 直接查找基于硬件的哈希表用于调用返回缓存。

公开(公告)号：US20090006750A1

公开(公告)日：2009-01-01

申请号：US11823224

申请日：2007-06-27

申请人： Martin Taillefer ,  Darek Mihocka ,  Bruno Silva

发明人： Martin Taillefer ,  Darek Mihocka ,  Bruno Silva

IPC分类号： G06F12/00

CPC分类号： G06F9/45533 ,  G06F9/45504 ,  G06F9/45516 ,  G06F9/466

摘要： Various technologies and techniques are disclosed for using transactional memory hardware to accelerate virtualization or emulation. State isolation can be facilitated by providing isolated private state on transactional memory hardware and storing the stack of a host that is performing an emulation in the isolated private state. Memory accesses performed by a central processing unit can be monitored by software to detect that a guest being emulated has made a self modification to its own code sequence. Transactional memory hardware can be used to facilitate dispatch table updates in multithreaded environments by taking advantage of the atomic commit feature. An emulator is provided that uses a dispatch table stored in main memory to convert a guest program counter into a host program counter. The dispatch table is accessed to see if the dispatch table contains a particular host program counter for a particular guest program counter.

摘要翻译： 公开了用于使用事务性存储器硬件来加速虚拟化或仿真的各种技术和技术。 通过在事务性存储器硬件上提供隔离的私有状态并将执行仿真的主机的堆栈存储在隔离的私有状态中，可以促进状态隔离。 由中央处理单元执行的存储器访问可以被软件监视，以检测被仿真的客户对其自己的代码序列进行了自我修改。 事务存储器硬件可以用于通过利用原子提交功能来促进多线程环境中的调度表更新。 提供了一个仿真器，它使用存储在主存储器中的调度表将客户机程序计数器转换为主机程序计数器。 访问调度表以查看分派表是否包含特定客户机程序计数器的特定主机程序计数器。

公开(公告)号：US09043553B2

公开(公告)日：2015-05-26

申请号：US11823224

申请日：2007-06-27

申请人： Martin Taillefer ,  Darek Mihocka ,  Bruno Silva

发明人： Martin Taillefer ,  Darek Mihocka ,  Bruno Silva

IPC分类号： G06F12/00 ,  G06F9/455 ,  G06F9/46

CPC分类号： G06F9/45533 ,  G06F9/45504 ,  G06F9/45516 ,  G06F9/466

摘要： Various technologies and techniques are disclosed for using transactional memory hardware to accelerate virtualization or emulation. State isolation can be facilitated by providing isolated private state on transactional memory hardware and storing the stack of a host that is performing an emulation in the isolated private state. Memory accesses performed by a central processing unit can be monitored by software to detect that a guest being emulated has made a self modification to its own code sequence. Transactional memory hardware can be used to facilitate dispatch table updates in multithreaded environments by taking advantage of the atomic commit feature. An emulator is provided that uses a dispatch table stored in main memory to convert a guest program counter into a host program counter. The dispatch table is accessed to see if the dispatch table contains a particular host program counter for a particular guest program counter.

公开(公告)号：US20090007107A1

公开(公告)日：2009-01-01

申请号：US11823212

申请日：2007-06-27

申请人： Martin Taillefer ,  Darek Mihocka ,  Bruno Silva

发明人： Martin Taillefer ,  Darek Mihocka ,  Bruno Silva

IPC分类号： G06F9/455 ,  G06F17/50

CPC分类号： G06F9/45533

摘要： Various technologies and techniques are disclosed for using transactional memory hardware to accelerate virtualization or emulation. One or more central processing units are provided with transactional memory hardware that is operable to accelerate virtualization. The transactional memory hardware has a facility to maintain private state, a facility to render memory accesses from other central processing units visible to software, and support for atomic commit of the private state. The transactional memory hardware can be used, for example, to facilitate emulation of precise exception semantics. The private state is operable to enable an emulated state to remain inconsistent with an architectural state and only synchronized on certain boundaries. An optimized sequence of instructions is executed using chunk-accurate simulation to try and achieve a same end effect.

摘要翻译： 公开了用于使用事务性存储器硬件来加速虚拟化或仿真的各种技术和技术。 一个或多个中央处理单元设置有可操作以加速虚拟化的事务存储器硬件。 事务性存储器硬件具有维护私有状态的功能，用于使得对软件可见的其它中央处理单元进行存储器访问的设施，以及对私有状态的原子提交的支持。 例如，可以使用事务性存储器硬件来促进精确异常语义的仿真。 私有状态可操作以使仿真状态与架构状态保持不一致，并且仅在某些边界上同步。 使用块精确模拟来执行优化的指令序列，以尝试并实现相同的最终效果。

公开(公告)号：US08266387B2

公开(公告)日：2012-09-11

申请号：US11823212

申请日：2007-06-27

申请人： Martin Taillefer ,  Darek Mihocka ,  Bruno Silva

发明人： Martin Taillefer ,  Darek Mihocka ,  Bruno Silva

IPC分类号： G06F12/00 ,  G06F9/445

CPC分类号： G06F9/45533

摘要： Various technologies and techniques are disclosed for using transactional memory hardware to accelerate virtualization or emulation. One or more central processing units are provided with transactional memory hardware that is operable to accelerate virtualization. The transactional memory hardware has a facility to maintain private state, a facility to render memory accesses from other central processing units visible to software, and support for atomic commit of the private state. The transactional memory hardware can be used, for example, to facilitate emulation of precise exception semantics. The private state is operable to enable an emulated state to remain inconsistent with an architectural state and only synchronized on certain boundaries. An optimized sequence of instructions is executed using chunk-accurate simulation to try and achieve a same end effect.

摘要翻译： 公开了用于使用事务性存储器硬件来加速虚拟化或仿真的各种技术和技术。 一个或多个中央处理单元设置有可操作以加速虚拟化的事务存储器硬件。 事务性存储器硬件具有维护私有状态的功能，用于使得对软件可见的其它中央处理单元进行存储器访问的设施，以及对私有状态的原子提交的支持。 例如，可以使用事务性存储器硬件来促进精确异常语义的仿真。 私有状态可操作以使仿真状态与架构状态保持不一致，并且仅在某些边界上同步。 使用块精确模拟来执行优化的指令序列，以尝试并实现相同的最终效果。

公开(公告)号：US20090265156A1

公开(公告)日：2009-10-22

申请号：US12105290

申请日：2008-04-18

申请人： Martin Taillefer ,  Darek Mihocka

发明人： Martin Taillefer ,  Darek Mihocka

IPC分类号： G06F9/44

CPC分类号： G06F9/45504 ,  G06F7/483

摘要： Simulating a processor based system includes simulating first processor actions at a first precision level and detecting a first trigger. The simulation is dynamically changed to a second precision level that is different than the first precision level based on the first trigger. Second processor actions are simulated at the second precision level.

摘要翻译： 模拟基于处理器的系统包括以第一精度级别模拟第一处理器动作并检测第一触发。 仿真动态地改变为与基于第一个触发的第一精度等级不同的第二精度级别。 第二处理器动作在第二精度级别进行模拟。

公开(公告)号：US08392929B2

公开(公告)日：2013-03-05

申请号：US12638031

申请日：2009-12-15

申请人： Martin Taillefer ,  Gad Sheaffer

发明人： Martin Taillefer ,  Gad Sheaffer

IPC分类号： G06F9/455

CPC分类号： G06F11/3648

摘要： One embodiment includes method acts for detecting race conditions. The method includes beginning a critical section, during which conflicting reads and writes should be detected to determine if a race condition has occurred. This is performed by executing at a thread one or more software instructions to place a software lock on data. As a result of executing one or more software instructions to place a software lock on data, several additional acts are performed. In particular, the thread places a software lock on the data locking the data for at least one of exclusive writes or reads by the thread. And, at a local cache memory local to the thread, the thread enters the thread's memory isolation mode enabling local hardware buffering of memory writes and monitoring of conflicting writes or reads to or from the cache memory to detect reads or writes by non-lock respecting agents.

摘要翻译： 一个实施例包括用于检测竞态条件的方法动作。 该方法包括开始关键部分，在此期间应检测到冲突的读取和写入，以确定是否发生了竞争条件。 这通过在线程执行一个或多个软件指令来执行以对软件锁定数据。 作为执行一个或多个软件指令以对数据进行软件锁定的结果，执行几个附加动作。 特别地，线程将软件锁定在锁定数据的数据上，用于线程的排他写入或读取中的至少一个。 而且，在线程本地的本地高速缓存中，线程进入线程的内存隔离模式，使内存写入能够进行本地硬件缓冲，并监视与高速缓冲存储器冲突的写入或读取，以通过非锁定来检测读取或写入 代理商