公开(公告)号：US08176253B2

公开(公告)日：2012-05-08

申请号：US11823236

申请日：2007-06-27

申请人： Martin Taillefer ,  Darek Mihocka ,  Bruno Silva

发明人： Martin Taillefer ,  Darek Mihocka ,  Bruno Silva

IPC分类号： G06F12/00 ,  G06F9/455 ,  G06F9/44

CPC分类号： G06F9/466 ,  G06F9/45504 ,  G06F9/45533 ,  G06F2209/521

摘要： Various technologies and techniques are disclosed for using transactional memory hardware to accelerate virtualization or emulation. A central processing unit is provided with the transactional memory hardware. Code backpatching can be facilitated by providing transactional memory hardware that supports a facility to maintain private memory state and an atomic commit feature. Changes made to certain code are stored in the private state facility. Backpatching changes are enacted by attempting to commit all the changes to memory at once using the atomic commit feature. An efficient call return stack can be provided by using transactional memory hardware. A call return cache stored in the private state facility captures a host address to return to after execution of a guest function completes. A direct-lookup hardware-based hash table is used for the call return cache.

摘要翻译： 公开了用于使用事务性存储器硬件来加速虚拟化或仿真的各种技术和技术。 中央处理单元设置有事务存储器硬件。 可以通过提供事务性存储器硬件来支持代码反向补丁，该硬件支持维护私有内存状态和原子提交功能的功能。 对某些代码所做的更改存储在私人状态设施中。 通过尝试使用原子提交功能一次性向内存提交所有更改来实现后期更改。 可以通过使用事务性存储器硬件来提供高效的回叫栈。 存储在私有状态设施中的调用返回缓存捕获主机地址以在执行客户机功能完成后返回。 直接查找基于硬件的哈希表用于调用返回缓存。

公开(公告)号：US20090006751A1

公开(公告)日：2009-01-01

申请号：US11823236

申请日：2007-06-27

申请人： Martin Taillefer ,  Darek Mihocka ,  Bruno Silva

发明人： Martin Taillefer ,  Darek Mihocka ,  Bruno Silva

IPC分类号： G06F12/00

CPC分类号： G06F9/466 ,  G06F9/45504 ,  G06F9/45533 ,  G06F2209/521

摘要： Various technologies and techniques are disclosed for using transactional memory hardware to accelerate virtualization or emulation. A central processing unit is provided with the transactional memory hardware. Code backpatching can be facilitated by providing transactional memory hardware that supports a facility to maintain private memory state and an atomic commit feature. Changes made to certain code are stored in the private state facility. Backpatching changes are enacted by attempting to commit all the changes to memory at once using the atomic commit feature. An efficient call return stack can be provided by using transactional memory hardware. A call return cache stored in the private state facility captures a host address to return to after execution of a guest function completes. A direct-lookup hardware-based hash table is used for the call return cache.

摘要翻译： 公开了用于使用事务性存储器硬件来加速虚拟化或仿真的各种技术和技术。 中央处理单元设置有事务存储器硬件。 可以通过提供事务性存储器硬件来支持代码反向补丁，该硬件支持维护私有内存状态和原子提交功能的功能。 对某些代码所做的更改存储在私人状态设施中。 通过尝试使用原子提交功能一次性向内存提交所有更改来实现后期更改。 可以通过使用事务性存储器硬件来提供高效的回叫栈。 存储在私有状态设施中的调用返回缓存捕获主机地址以在执行客户机功能完成后返回。 直接查找基于硬件的哈希表用于调用返回缓存。

公开(公告)号：US20090006750A1

公开(公告)日：2009-01-01

申请号：US11823224

申请日：2007-06-27

申请人： Martin Taillefer ,  Darek Mihocka ,  Bruno Silva

发明人： Martin Taillefer ,  Darek Mihocka ,  Bruno Silva

IPC分类号： G06F12/00

CPC分类号： G06F9/45533 ,  G06F9/45504 ,  G06F9/45516 ,  G06F9/466

摘要： Various technologies and techniques are disclosed for using transactional memory hardware to accelerate virtualization or emulation. State isolation can be facilitated by providing isolated private state on transactional memory hardware and storing the stack of a host that is performing an emulation in the isolated private state. Memory accesses performed by a central processing unit can be monitored by software to detect that a guest being emulated has made a self modification to its own code sequence. Transactional memory hardware can be used to facilitate dispatch table updates in multithreaded environments by taking advantage of the atomic commit feature. An emulator is provided that uses a dispatch table stored in main memory to convert a guest program counter into a host program counter. The dispatch table is accessed to see if the dispatch table contains a particular host program counter for a particular guest program counter.

摘要翻译： 公开了用于使用事务性存储器硬件来加速虚拟化或仿真的各种技术和技术。 通过在事务性存储器硬件上提供隔离的私有状态并将执行仿真的主机的堆栈存储在隔离的私有状态中，可以促进状态隔离。 由中央处理单元执行的存储器访问可以被软件监视，以检测被仿真的客户对其自己的代码序列进行了自我修改。 事务存储器硬件可以用于通过利用原子提交功能来促进多线程环境中的调度表更新。 提供了一个仿真器，它使用存储在主存储器中的调度表将客户机程序计数器转换为主机程序计数器。 访问调度表以查看分派表是否包含特定客户机程序计数器的特定主机程序计数器。

公开(公告)号：US20090007107A1

公开(公告)日：2009-01-01

申请号：US11823212

申请日：2007-06-27

申请人： Martin Taillefer ,  Darek Mihocka ,  Bruno Silva

发明人： Martin Taillefer ,  Darek Mihocka ,  Bruno Silva

IPC分类号： G06F9/455 ,  G06F17/50

CPC分类号： G06F9/45533

摘要： Various technologies and techniques are disclosed for using transactional memory hardware to accelerate virtualization or emulation. One or more central processing units are provided with transactional memory hardware that is operable to accelerate virtualization. The transactional memory hardware has a facility to maintain private state, a facility to render memory accesses from other central processing units visible to software, and support for atomic commit of the private state. The transactional memory hardware can be used, for example, to facilitate emulation of precise exception semantics. The private state is operable to enable an emulated state to remain inconsistent with an architectural state and only synchronized on certain boundaries. An optimized sequence of instructions is executed using chunk-accurate simulation to try and achieve a same end effect.

摘要翻译： 公开了用于使用事务性存储器硬件来加速虚拟化或仿真的各种技术和技术。 一个或多个中央处理单元设置有可操作以加速虚拟化的事务存储器硬件。 事务性存储器硬件具有维护私有状态的功能，用于使得对软件可见的其它中央处理单元进行存储器访问的设施，以及对私有状态的原子提交的支持。 例如，可以使用事务性存储器硬件来促进精确异常语义的仿真。 私有状态可操作以使仿真状态与架构状态保持不一致，并且仅在某些边界上同步。 使用块精确模拟来执行优化的指令序列，以尝试并实现相同的最终效果。

公开(公告)号：US09043553B2

公开(公告)日：2015-05-26

申请号：US11823224

申请日：2007-06-27

申请人： Martin Taillefer ,  Darek Mihocka ,  Bruno Silva

发明人： Martin Taillefer ,  Darek Mihocka ,  Bruno Silva

IPC分类号： G06F12/00 ,  G06F9/455 ,  G06F9/46

CPC分类号： G06F9/45533 ,  G06F9/45504 ,  G06F9/45516 ,  G06F9/466

摘要： Various technologies and techniques are disclosed for using transactional memory hardware to accelerate virtualization or emulation. State isolation can be facilitated by providing isolated private state on transactional memory hardware and storing the stack of a host that is performing an emulation in the isolated private state. Memory accesses performed by a central processing unit can be monitored by software to detect that a guest being emulated has made a self modification to its own code sequence. Transactional memory hardware can be used to facilitate dispatch table updates in multithreaded environments by taking advantage of the atomic commit feature. An emulator is provided that uses a dispatch table stored in main memory to convert a guest program counter into a host program counter. The dispatch table is accessed to see if the dispatch table contains a particular host program counter for a particular guest program counter.

公开(公告)号：US08266387B2

公开(公告)日：2012-09-11

申请号：US11823212

申请日：2007-06-27

申请人： Martin Taillefer ,  Darek Mihocka ,  Bruno Silva

发明人： Martin Taillefer ,  Darek Mihocka ,  Bruno Silva

IPC分类号： G06F12/00 ,  G06F9/445

CPC分类号： G06F9/45533

摘要： Various technologies and techniques are disclosed for using transactional memory hardware to accelerate virtualization or emulation. One or more central processing units are provided with transactional memory hardware that is operable to accelerate virtualization. The transactional memory hardware has a facility to maintain private state, a facility to render memory accesses from other central processing units visible to software, and support for atomic commit of the private state. The transactional memory hardware can be used, for example, to facilitate emulation of precise exception semantics. The private state is operable to enable an emulated state to remain inconsistent with an architectural state and only synchronized on certain boundaries. An optimized sequence of instructions is executed using chunk-accurate simulation to try and achieve a same end effect.

摘要翻译： 公开了用于使用事务性存储器硬件来加速虚拟化或仿真的各种技术和技术。 一个或多个中央处理单元设置有可操作以加速虚拟化的事务存储器硬件。 事务性存储器硬件具有维护私有状态的功能，用于使得对软件可见的其它中央处理单元进行存储器访问的设施，以及对私有状态的原子提交的支持。 例如，可以使用事务性存储器硬件来促进精确异常语义的仿真。 私有状态可操作以使仿真状态与架构状态保持不一致，并且仅在某些边界上同步。 使用块精确模拟来执行优化的指令序列，以尝试并实现相同的最终效果。

公开(公告)号：US20100332808A1

公开(公告)日：2010-12-30

申请号：US12493168

申请日：2009-06-26

申请人： Ali-Reza Adl-Tabatabai ,  Bratin Saha ,  Gad Sheaffer ,  Vadim Bassin ,  Robert Y. Geva ,  Martin Taillefer ,  Darek Mihocka ,  Burton Jordan Smith ,  Jan Gray

发明人： Ali-Reza Adl-Tabatabai ,  Bratin Saha ,  Gad Sheaffer ,  Vadim Bassin ,  Robert Y. Geva ,  Martin Taillefer ,  Darek Mihocka ,  Burton Jordan Smith ,  Jan Gray

IPC分类号： G06F9/30 ,  G06F9/312

CPC分类号： G06F9/3004 ,  G06F9/30076 ,  G06F9/30087 ,  G06F9/30101 ,  G06F9/30181 ,  G06F9/30189 ,  G06F9/3857 ,  G06F9/467

摘要： Minimizing code duplication in an unbounded transactional memory system. A computing apparatus including one or more processors in which it is possible to use a set of common mode-agnostic TM barrier sequences that runs on legacy ISA and extended ISA processors, and that employs hardware filter indicators (when available) to filter redundant applications of TM barriers, and that enables a compiled binary representation of the subject code to run correctly in any of the currently implemented set of transactional memory execution modes, including running the code outside of a transaction, and that enables the same compiled binary to continue to work with future TM implementations which may introduce as yet unknown future TM execution modes.

摘要翻译： 最大限度地减少无界事务内存系统中的代码重复。 一种包括一个或多个处理器的计算设备，其中可以使用在传统ISA和扩展ISA处理器上运行的一组共同模式不可知TM屏障序列，并且采用硬件滤波器指示器（当可用时）可以过滤冗余应用 TM屏障，并且使得主体代码的编译二进制表示可以在任何当前实现的事务存储器执行模式集中运行，包括在事务之外运行代码，并且使得相同的编译的二进制文件能够继续工作 与未来的TM实现可能会引入未知的未来TM执行模式。

公开(公告)号：US08473921B2

公开(公告)日：2013-06-25

申请号：US12646438

申请日：2009-12-23

申请人： Martin Taillefer ,  Ali-Reza Adl-Tabatabai ,  Gad Sheaffer ,  Peter Lachner ,  Richard Wurdack ,  Darek Mihocka ,  Jan Gray

发明人： Martin Taillefer ,  Ali-Reza Adl-Tabatabai ,  Gad Sheaffer ,  Peter Lachner ,  Richard Wurdack ,  Darek Mihocka ,  Jan Gray

IPC分类号： G06F9/44

CPC分类号： G06F11/362 ,  G06F12/0817

摘要： Debugging software in systems with architecturally significant processor caches. A method may be practiced in a computing environment. The method includes acts for debugging a software application, wherein the software application is configured to use one or more architecturally significant processor caches coupled to a processor. The method includes beginning execution of the software application. A debugger is run while executing the software application. The software application causes at least one of reads or writes to be made to the cache in an architecturally significant fashion. The reads or writes made to the cache in an architecturally significant fashion are preserved while performing debugging operations that would ordinarily disturb the reads or writes made to the cache in an architecturally significant fashion.

摘要翻译： 在具有架构上重要的处理器高速缓存的系统中调试软件。 可以在计算环境中实施一种方法。 该方法包括用于调试软件应用程序的动作，其中软件应用被配置为使用耦合到处理器的一个或多个架构上重要的处理器高速缓存。 该方法包括开始执行软件应用程序。 在执行软件应用程序时运行调试器。 软件应用程序使得以架构上显着的方式对缓存进行读取或写入中的至少一个。 以架构上显着的方式对高速缓存进行的读取或写入被保留，同时执行调整操作，这些调试操作通常会以建筑上重要的方式干扰对高速缓存的读取或写入。

公开(公告)号：US08356166B2

公开(公告)日：2013-01-15

申请号：US12493168

申请日：2009-06-26

申请人： Ali-Reza Adl-Tabatabai ,  Bratin Saha ,  Gad Sheaffer ,  Vadim Bassin ,  Robert Y. Geva ,  Martin Taillefer ,  Darek Mihocka ,  Burton Jordan Smith ,  Jan Gray

发明人： Ali-Reza Adl-Tabatabai ,  Bratin Saha ,  Gad Sheaffer ,  Vadim Bassin ,  Robert Y. Geva ,  Martin Taillefer ,  Darek Mihocka ,  Burton Jordan Smith ,  Jan Gray

IPC分类号： G06F15/00 ,  G06F9/00 ,  G06F9/44 ,  G06F7/38

CPC分类号： G06F9/3004 ,  G06F9/30076 ,  G06F9/30087 ,  G06F9/30101 ,  G06F9/30181 ,  G06F9/30189 ,  G06F9/3857 ,  G06F9/467

摘要： Minimizing code duplication in an unbounded transactional memory system. A computing apparatus including one or more processors in which it is possible to use a set of common mode-agnostic TM barrier sequences that runs on legacy ISA and extended ISA processors, and that employs hardware filter indicators (when available) to filter redundant applications of TM barriers, and that enables a compiled binary representation of the subject code to run correctly in any of the currently implemented set of transactional memory execution modes, including running the code outside of a transaction, and that enables the same compiled binary to continue to work with future TM implementations which may introduce as yet unknown future TM execution modes.

摘要翻译： 最大限度地减少无界事务内存系统中的代码重复。 一种包括一个或多个处理器的计算设备，其中可以使用在传统ISA和扩展ISA处理器上运行的一组共同模式不可知TM屏障序列，并且采用硬件滤波器指示器（当可用时）可以过滤冗余应用 TM屏障，并且使得主体代码的编译二进制表示可以在任何当前实现的事务存储器执行模式集中运行，包括在事务之外运行代码，并且使得相同的编译的二进制文件能够继续工作 与未来的TM实现可能会引入未知的未来TM执行模式。

公开(公告)号：US20110145798A1

公开(公告)日：2011-06-16

申请号：US12646438

申请日：2009-12-23

申请人： Martin Taillefer ,  Ali-Reza Adl-Tabatabai ,  Gad Sheaffer ,  Peter Lachner ,  Richard Wurdack ,  Darek Mihocka ,  Jan Gray

发明人： Martin Taillefer ,  Ali-Reza Adl-Tabatabai ,  Gad Sheaffer ,  Peter Lachner ,  Richard Wurdack ,  Darek Mihocka ,  Jan Gray

IPC分类号： G06F9/44 ,  G06F15/76

CPC分类号： G06F11/362 ,  G06F12/0817

摘要： Debugging software in systems with architecturally significant processor caches. A method may be practiced in a computing environment. The method includes acts for debugging a software application, wherein the software application is configured to use one or more architecturally significant processor caches coupled to a processor. The method includes beginning execution of the software application. A debugger is run while executing the software application. The software application causes at least one of reads or writes to be made to the cache in an architecturally significant fashion. The reads or writes made to the cache in an architecturally significant fashion are preserved while performing debugging operations that would ordinarily disturb the reads or writes made to the cache in an architecturally significant fashion.

摘要翻译： 在具有架构上重要的处理器高速缓存的系统中调试软件。 可以在计算环境中实施一种方法。 该方法包括用于调试软件应用程序的动作，其中软件应用被配置为使用耦合到处理器的一个或多个架构上重要的处理器高速缓存。 该方法包括开始执行软件应用程序。 在执行软件应用程序时运行调试器。 软件应用程序使得以架构上显着的方式对缓存进行读取或写入中的至少一个。 以架构上显着的方式对高速缓存进行的读取或写入被保留，同时执行调整操作，这些调试操作通常会以建筑上重要的方式干扰对高速缓存的读取或写入。