公开(公告)号：US11568930B2

公开(公告)日：2023-01-31

申请号：US17484136

申请日：2021-09-24

Applicant: Micron Technology, Inc.

Inventor： John Christopher Sancon

IPC: G11C11/00 ,  G11C13/00

Abstract: Memory devices may have an array of elements in two or more dimensions. The memory devices use multiple access lines arranged in a grid to access the memory devices. Memory cells located at intersections of the access lines in the grid. Drivers are used for each access line and configured to transmit a corresponding signal to respective memory cells of the plurality of memory cells via a corresponding access line. The memory devices uses an electrical distance calculator to determine an electrical distance from a memory cell to a respective driver of the plurality of drivers. The memory device also uses a driver modulator to modulate the corresponding signal based at least in part on the electrical distance.

公开(公告)号：US20220415395A1

公开(公告)日：2022-12-29

申请号：US17865248

申请日：2022-07-14

Applicant: Micron Technology, Inc.

Inventor： Joemar Sinipete ,  John Christopher Sancon ,  Mingdong Cui

IPC: G11C13/00

Abstract: Methods, systems, and devices for a refresh operation of a memory cell are described. A memory device may include a plurality of rows of memory cells. Each row of memory cells may undergo a quantity of access operations (e.g., read operations, write operations). During a read operation, a logic state of one or more memory cells may be determined by applying a read pulse having a first polarity. Based on the one or more memory cells storing a particular logic state (e.g., a first logic state), a refresh operation may be performed. During a refresh operation, a refresh pulse having a second polarity (e.g., a different polarity than the first polarity) may be applied to the one or more memory cells.

公开(公告)号：US20210398590A1

公开(公告)日：2021-12-23

申请号：US17328809

申请日：2021-05-24

Applicant: Micron Technology, Inc.

Inventor： John Christopher Sancon

IPC: G11C13/00

Abstract: Memory devices have an array of elements in two or more dimensions. The memory devices use multiple access lines arranged in a grid to access the memory devices. Memory cells are located at intersections of the access lines in the grid. Drivers are used for each access line and configured to transmit a corresponding signal to respective memory cells of the plurality of memory cells via a corresponding access line. The memory devices also include compensation circuitry configured to determine which driving access lines driving a target memory cell of the plurality of memory cells has the most distance between the target memory cell and a respective driver. The plurality of access lines comprise the driving access lines. The compensation circuitry also is configured to output compensation values to adjust the voltages of the driving access lines based on a polarity of the voltage of the longer driving access line.

公开(公告)号：US11170851B1

公开(公告)日：2021-11-09

申请号：US16903921

申请日：2020-06-17

Applicant: Micron Technology, Inc.

Inventor： John Christopher Sancon

IPC: G11C8/00 ,  G11C13/00

Abstract: Memory devices may have an array of elements in two or more dimensions. The memory devices use multiple access lines arranged in a grid to access the memory devices. Memory cells located at intersections of the access lines in the grid. Drivers are used for each access line and configured to transmit a corresponding signal to respective memory cells of the plurality of memory cells via a corresponding access line. The memory devices uses an electrical distance calculator to determine an electrical distance from a memory cell to a respective driver of the plurality of drivers. The memory device also uses a driver modulator to modulate the corresponding signal based at least in part on the electrical distance.