公开(公告)号：US20250156351A1

公开(公告)日：2025-05-15

申请号：US18908554

申请日：2024-10-07

Applicant: Micron Technology, Inc.

Inventor： John Christopher Sancon

IPC: G06F13/18 ,  G06F13/16

Abstract: A memory module control hub includes a first priority logic circuit configured to receive an in-band interrupt (IBI) message from a memory device having a unique identifier and configured to set a first priority flag based on a category of the IBI message, and a second priority logic circuit configured to receive the IBI message from the memory device and configured to set a second priority flag based on the category of the IBI message. The memory module control hub further includes a dynamic identifier assignment circuit configured to adjust priority bits of the unique identifier based on whether the first or second priority flags are set.

公开(公告)号：US11798622B2

公开(公告)日：2023-10-24

申请号：US17865248

申请日：2022-07-14

Applicant: Micron Technology, Inc.

Inventor： Joemar Sinipete ,  John Christopher Sancon ,  Mingdong Cui

IPC: G11C11/00 ,  G11C13/00

CPC classification number: G11C13/0097 ,  G11C13/0004 ,  G11C13/004 ,  G11C13/0033 ,  G11C13/0069 ,  G11C2013/0045 ,  G11C2013/0078

Abstract: Methods, systems, and devices for a refresh operation of a memory cell are described. A memory device may include a plurality of rows of memory cells. Each row of memory cells may undergo a quantity of access operations (e.g., read operations, write operations). During a read operation, a logic state of one or more memory cells may be determined by applying a read pulse having a first polarity. Based on the one or more memory cells storing a particular logic state (e.g., a first logic state), a refresh operation may be performed. During a refresh operation, a refresh pulse having a second polarity (e.g., a different polarity than the first polarity) may be applied to the one or more memory cells.

公开(公告)号：US20240347096A1

公开(公告)日：2024-10-17

申请号：US18628127

申请日：2024-04-05

Applicant: Micron Technology, Inc.

Inventor： Yang Lu ,  Mark Kalei Hadrick ,  HyunYoo Lee ,  KeunSoo Song ,  John Christopher Sancon ,  Kang-Yong Kim

IPC: G11C11/406 ,  G11C11/4096

CPC classification number: G11C11/40615 ,  G11C11/40611 ,  G11C11/4096

Abstract: Apparatuses and techniques for implementing usage-based disturbance counter clearance are described. In example implementations, a memory device includes a memory array having multiple rows. The memory device also includes multiple usage-based disturbance counters that are associated with the memory array. The memory device further includes logic that performs a refresh operation on a row of the multiple rows responsive to a refresh command. The logic also clears a usage-based disturbance counter of the multiple usage-based disturbance counters responsive to the refresh command. Here, the usage-based disturbance counter stores a quantity of accesses to the row of the multiple rows. This can reduce a frequency of performing usage-based disturbance mitigation procedures that would otherwise be applied to the multiple usage-based disturbance counters, thereby saving power and avoiding denial-of-service periods with the memory array.

公开(公告)号：US11837286B2

公开(公告)日：2023-12-05

申请号：US18046393

申请日：2022-10-13

Applicant: Micron Technology, Inc.

Inventor： John Christopher Sancon

IPC: G11C11/00 ,  G11C13/00

CPC classification number: G11C13/003 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/0004 ,  G11C13/0011

Abstract: Memory devices have an array of elements in two or more dimensions. The memory devices use multiple access lines arranged in a grid to access the memory devices. Memory cells are located at intersections of the access lines in the grid. Drivers are used for each access line and configured to transmit a corresponding signal to respective memory cells of the plurality of memory cells via a corresponding access line. The memory devices also include compensation circuitry configured to determine which driving access lines driving a target memory cell of the plurality of memory cells has the most distance between the target memory cell and a respective driver. The plurality of access lines comprise the driving access lines. The compensation circuitry also is configured to output compensation values to adjust the voltages of the driving access lines based on a polarity of the voltage of the longer driving access line.

公开(公告)号：US20230343381A1

公开(公告)日：2023-10-26

申请号：US17660199

申请日：2022-04-21

Applicant: Micron Technology, Inc.

Inventor： John Christopher Sancon ,  Yang Lu ,  Kang-Yong Kim ,  Mark Kalei Hadrick ,  Hyun Yoo Lee

IPC: G11C11/406 ,  G11C11/4076 ,  G11C11/408

CPC classification number: G11C11/40618 ,  G11C11/40615 ,  G11C11/4076 ,  G11C11/4085

Abstract: Described apparatuses and methods relate to a bank-level self-refresh for a memory system. A memory device can include logic that implements self-refresh operations in the memory device. The logic may perform self-refresh operations on a set of banks of the memory device that is less than all banks within the memory device. The set of banks of the memory device may be determined such that the peak current in a power distribution network of the memory device is bounded when the self-refresh operation is performed. Accordingly, bank-level self-refresh can reduce a cost of the memory device of a memory system by enabling use of a less complicated power distribution network. The bank-level self-refresh may also be implemented with different types of refresh operations. Amongst other scenarios, bank-level self-refresh can be deployed in memory-expansion environments.

公开(公告)号：US12235784B2

公开(公告)日：2025-02-25

申请号：US17823423

申请日：2022-08-30

Applicant: Micron Technology, Inc.

Inventor： Yang Lu ,  Creston M. Dupree ,  Smruti Subhash Jhaveri ,  Hyun Yoo Lee ,  John Christopher Sancon ,  Kang-Yong Kim ,  Francesco Douglas Verna-Ketel

IPC: G06F13/40 ,  G06F13/16

Abstract: Described apparatuses and methods facilitate bus training with multiple dice, such as multiple memory dice. A controller can communicate with multiple dice to perform bus training by sending a test pattern and receiving in return a feedback pattern indicative of the bits detected by the dice. Because suitable signal timing can differ between dice, even those using the same bus, a controller may train each die separately from the others. In some situations, however, individualized training may be infeasible. To accommodate such situations, logic associated with two or more dice can combine, using at least one logical operation, bits as detected from the test pattern into a combined feedback pattern. A timing parameter that is jointly suitable for multiple dice can be determined, and the bus training may be concluded, responsive to the combined feedback pattern matching the test pattern. The multiple dice may be stacked or linked.

公开(公告)号：US12223995B2

公开(公告)日：2025-02-11

申请号：US17823407

申请日：2022-08-30

Applicant: Micron Technology, Inc.

Inventor： John Christopher Sancon ,  Kang-Yong Kim ,  Yang Lu ,  Hyun Yoo Lee

IPC: G11C11/406 ,  G11C11/4096

Abstract: Described apparatuses and methods relate to adaptive memory registers for a memory system that may support a nondeterministic protocol. To help manage power-delivery networks in a memory system, a device includes logic that can write values to memory registers associated with memory blocks of a memory array. The values indicate whether an associated memory block has been refreshed within a refresh interval. Other logic can read the registers to determine whether a block has been refreshed. The device also includes logic that can access data indicating a row address that was most recently, or is next to be, refreshed and write values representing the address to another register. The register can be read by other logic to determine whether a wordline potentially affected by an activation-based disturb event is near to being refreshed. These techniques can reduce the number of refresh operations performed, saving power and reducing costs.

公开(公告)号：US12204780B2

公开(公告)日：2025-01-21

申请号：US17660195

申请日：2022-04-21

Applicant: Micron Technology, Inc.

Inventor： Mark Kalei Hadrick ,  Yu-Sheng Hsu ,  John Christopher Sancon ,  Kang-Yong Kim ,  Yang Lu

IPC: G06F3/06

Abstract: Described apparatuses and methods relate to self-refresh arbitration. In a memory system with multiple memory components, an arbiter is configured to manage the occurrence of self-refresh operations. In aspects, the arbiter can receive one or more self-refresh request signals from at least one memory controller for authorization to command one or more memory components to enter a self-refresh mode. Upon receiving the one or more self-refresh request signals, the arbiter, based on a predetermined configuration, can transmit one or more self-refresh enable signals to the at least one memory controller with authorization to command the one or more memory components to enter the self-refresh mode. The configuration can ensure that fewer than all memory components simultaneously enter the self-refresh mode. In so doing, memory components can perform self-refresh operations without exceeding an instantaneous power threshold. The arbiter can be included in, for instance, a Compute Express Link™ (CXL™) memory module.

公开(公告)号：US20220013168A1

公开(公告)日：2022-01-13

申请号：US17484136

申请日：2021-09-24

Applicant: Micron Technology, Inc.

Inventor： John Christopher Sancon

IPC: G11C13/00

Abstract: Memory devices may have an array of elements in two or more dimensions. The memory devices use multiple access lines arranged in a grid to access the memory devices. Memory cells located at intersections of the access lines in the grid. Drivers are used for each access line and configured to transmit a corresponding signal to respective memory cells of the plurality of memory cells via a corresponding access line. The memory devices uses an electrical distance calculator to determine an electrical distance from a memory cell to a respective driver of the plurality of drivers. The memory device also uses a driver modulator to modulate the corresponding signal based at least in part on the electrical distance.

公开(公告)号：US20240071461A1

公开(公告)日：2024-02-29

申请号：US17823407

申请日：2022-08-30

Applicant: Micron Technology, Inc.

Inventor： John Christopher Sancon ,  Kang-Yong Kim ,  Yang Lu ,  Hyun Yoo Lee

IPC: G11C11/406 ,  G11C11/4096

CPC classification number: G11C11/40622 ,  G11C11/40615 ,  G11C11/4096

Abstract: Described apparatuses and methods relate to adaptive memory registers for a memory system that may support a nondeterministic protocol. To help manage power-delivery networks in a memory system, a device includes logic that can write values to memory registers associated with memory blocks of a memory array. The values indicate whether an associated memory block has been refreshed within a refresh interval. Other logic can read the registers to determine whether a block has been refreshed. The device also includes logic that can access data indicating a row address that was most recently, or is next to be, refreshed and write values representing the address to another register. The register can be read by other logic to determine whether a wordline potentially affected by an activation-based disturb event is near to being refreshed. These techniques can reduce the number of refresh operations performed, saving power and reducing costs.