公开(公告)号：US20240201850A1

公开(公告)日：2024-06-20

申请号：US18383761

申请日：2023-10-25

Applicant: Micron Technology, Inc.

Inventor： Nitul Gohain ,  Nicola Colella

IPC: G06F3/06

CPC classification number: G06F3/0608 ,  G06F3/0604 ,  G06F3/0643 ,  G06F3/0679

Abstract: Aspects of the present disclosure configure a system component, such as a memory sub-system controller, to provide media fragmentation management. The controller receives, from a host, a file-based-optimization (FBO) entry comprising a plurality of logical block addresses (LBAs) associated with a file. The controller accesses a page table that associates the plurality of LBAs with respective physical addresses of a set of memory components and determines a first quantity of read operations that need to be performed to read data from the physical addresses of the set of memory components associated with the plurality of LBAs. The controller computes a regression level for the file based on the first quantity of read operations relative to a second quantity of LBAs included in the plurality of LBAs.

公开(公告)号：US20240176701A1

公开(公告)日：2024-05-30

申请号：US18519458

申请日：2023-11-27

Applicant: Micron Technology, Inc.

Inventor： Nitul Gohain ,  Jameer Mulani ,  Jonathan S. Parry

IPC: G06F11/10 ,  G06F11/07

CPC classification number: G06F11/1068 ,  G06F11/0757 ,  G06F11/0772

Abstract: Methods, systems, and devices to enhance read performance for memory data word decoding using power allocation based on error pattern detection in both QLC and TLC in both QLC and TLC products are described. A plurality of data words may be processed using a first decoder engine of a decoder of a memory device according to a first power setting. The decoder may detect a pattern of errors in the plurality of data words. The decoder may further communicate a status signal based on detecting the pattern of errors. The resource manager may allocate based on the status signal, a second amount of power credits to the decoder. The decoder may process a portion of the plurality of data words using a second decoder engine according to the second amount of power credits.

公开(公告)号：US11940874B2

公开(公告)日：2024-03-26

申请号：US17883051

申请日：2022-08-08

Applicant: Micron Technology, Inc.

Inventor： Nitul Gohain ,  Jonathan S. Parry ,  Reshmi Basu

IPC: G06F11/10 ,  G06F3/06 ,  G06F11/07

CPC classification number: G06F11/1068 ,  G06F3/0619 ,  G06F3/0659 ,  G06F3/0679 ,  G06F11/0772

Abstract: Methods, systems, and devices for queue management for a memory system are described. The memory system may include a first decoder associated with a first error control capability and a second decoder associated with a second error control capability. The memory system may receive a command and identify an expected latency for performing an error control operation on the command. The memory system may determine whether to assign the command to a first queue associated with the first decoder or a second queue associated with the second decoder based at least in part on the expected latency for processing the command using the first decoder. Upon assigning the command to a decoder, the command may be processed by the first queue or the second queue.

公开(公告)号：US20230393934A1

公开(公告)日：2023-12-07

申请号：US17804826

申请日：2022-05-31

Applicant: Micron Technology, Inc.

Inventor： Nitul Gohain ,  Giuseppe Cariello ,  Jameer Mulani

IPC: G06F11/10 ,  G06F11/07 ,  G06F3/06

CPC classification number: G06F11/1068 ,  G06F11/0757 ,  G06F11/076 ,  G06F3/0679 ,  G06F3/0619 ,  G06F3/0632 ,  G06F3/0659 ,  G06F11/0772

Abstract: Methods, systems, and devices for determining locations in memory for boot-up code are described. An indication of one or more timeout durations for a boot sequence is received. Information for the boot sequence is stored in one or more memory cells based on the one or more timeout durations, where the one or more memory cells is selected based on a read latency, an error rate, or a storage-level of the one or more memory cells with relation to the indicated one or more timeout durations. The information for the boot sequence stored in the one or more memory cells is accessed based on an initialization of the boot sequence.