BUS DEVICE AND METHOD FOR OPERATING A BUS DEVICE

    公开(公告)号:US20200250127A1

    公开(公告)日:2020-08-06

    申请号:US16775170

    申请日:2020-01-28

    Applicant: NXP B.V.

    Abstract: The present disclosure relates to a bus device and a corresponding bus system. Furthermore, the present disclosure relates to a corresponding method of operating a bus device.In accordance with a first aspect of the present disclosure there is provided a bus device comprising a bus protocol controller with a transmit data output and a bus transceiver with a transmit data input coupled to the transmit data output of the bus protocol controller, wherein the bus protocol controller is configured to provide a serial bit stream designated for transmission through a bus via the transmit data output of the bus controller and via the transmit data input to the bus transceiver and to provide a switching signal within the serial bit stream, and wherein the bus transceiver is configured to switch between different operating modes in response to the switching signal.

    Method and device for communicating data frames on a multi-master bus

    公开(公告)号:US10439840B1

    公开(公告)日:2019-10-08

    申请号:US16048159

    申请日:2018-07-27

    Applicant: NXP B.V.

    Abstract: Embodiments of a device and method are disclosed. In an embodiment, a method for communicating data frames on a bus that operates according to a multi-master bus protocol is disclosed. The method involves beginning transmission of a data frame from a node on the bus when the node gains control of the bus, wherein the multi-master bus protocol specifies a frame format that includes a start portion, a payload portion, and an end portion, during transmission of the payload portion of the data frame, inserting an in-payload arbitration field into the transmission, continuing transmission of the data frame if the node maintains control of the bus after insertion of the in-payload arbitration field, and halting transmission of the data frame before transmission of the data frame is complete if the node losses control of the bus after insertion of the in-payload arbitration field.

    Apparatus for a controller area network

    公开(公告)号:US12206521B2

    公开(公告)日:2025-01-21

    申请号:US18066018

    申请日:2022-12-14

    Applicant: NXP B.V.

    Abstract: An apparatus for a CAN transceiver configured to couple to a CAN bus and generate receive-data based on signals therefrom and generate signals on the CAN bus in response to transmit-data received from a CAN controller, wherein the apparatus is configured to: receive the receive-data comprising a plurality of bits; and for each of one or more bits of the receive-data, sample at a respective sample time to determine a respective value of each of the one or more bits; and with an edge detector determine, during a respective edge detector window, the occurrence of an edge in the receive-data and generate metadata indicative thereof, wherein the edge detector window comprises a period of time that includes the sample time; and wherein the apparatus is configured to determine whether transmit-data is compliant with one or more rules based on the respective values and the metadata.

    DELAY MODULE FOR A CONTROLLER AREA NETWORK (CAN), A CAN DEVICE, AND A METHOD FOR THE DELAY MODULE

    公开(公告)号:US20240356773A1

    公开(公告)日:2024-10-24

    申请号:US18638086

    申请日:2024-04-17

    Applicant: NXP B.V.

    CPC classification number: H04L12/40013 G06F11/0745 H04L2012/40215

    Abstract: The invention relates to a delay module for a CAN device. The delay module is configured to delay only a single signal change of an RXD signal, wherein the single signal change forms the end of an idle state. Use of the delay module allows a second RXD signal to be generated. The invention further relates to a CAN device comprising two CAN controllers. Each of the two CAN controllers may be provided with one of the two RXD signals. The CAN device may further be configured to detect possible errors based on the decoded bits of the RXD signals. As a result, the CAN device can communicate error-free with both distantly located further CAN devices and closely located further CAN devices, while ensuring a high data rate. The invention also relates to a method for the delay module.

    Controller area network device
    26.
    发明授权

    公开(公告)号:US11789886B2

    公开(公告)日:2023-10-17

    申请号:US17657069

    申请日:2022-03-29

    Applicant: NXP B.V.

    CPC classification number: G06F13/4068 H04L12/40 H04L2012/40215

    Abstract: A Controller Area Network, CAN, device comprising: a compare module configured to interface with a CAN transceiver, a CAN decoder configured to decode an identifier of a CAN message received from the RXD input interface; an identifier memory configured to store an entry that corresponds to at least one identifier; compare logic configured to compare a received identifier from a CAN message to the entry that is stored in the identifier memory and to output a match signal upon a match; a signal generator configured to output, in response to the match signal, a signal to invalidate the CAN message, wherein the signal is output from the TXD output interface to the CAN transceiver; and wherein the signal generated by the signal generator provides for one or more dominant bits that are timed so that at a bit immediately following a FDF field or the FDF field bit is made dominant.

    CONTROLLER AREA NETWORK DEVICE
    27.
    发明申请

    公开(公告)号:US20220318178A1

    公开(公告)日:2022-10-06

    申请号:US17657069

    申请日:2022-03-29

    Applicant: NXP B.V.

    Abstract: A Controller Area Network, CAN, device comprising: a compare module configured to interface with a CAN transceiver, a CAN decoder configured to decode an identifier of a CAN message received from the RXD input interface; an identifier memory configured to store an entry that corresponds to at least one identifier; compare logic configured to compare a received identifier from a CAN message to the entry that is stored in the identifier memory and to output a match signal upon a match; a signal generator configured to output, in response to the match signal, a signal to invalidate the CAN message, wherein the signal is output from the TXD output interface to the CAN transceiver; and wherein the signal generated by the signal generator provides for one or more dominant bits that are timed so that at a bit immediately following a FDF field or the FDF field bit is made dominant.

    SECURITY MODULE FOR A SERIAL COMMUNICATIONS DEVICE

    公开(公告)号:US20210044382A1

    公开(公告)日:2021-02-11

    申请号:US16984699

    申请日:2020-08-04

    Applicant: NXP B.V.

    Abstract: A security module (434) for a serial communications device. The security module (434) comprising: a receive data, RXD, input interface (436) for receiving data from a serial communications bus (404); and a transmit data, TXD, output interface (438) for transmitting data to the serial communications bus (404). The security module (434) is configured to: receive a message (540) from the serial communications bus (404) via the RXD input interface (436); compare the message (540) with one or more error conditions; and upon detection that an error condition has been violated, output an error-signal (543) to the serial communications bus (404) via the TXD output interface (438), wherein the error-signal (543) identifies one or more parameters relating to the error condition.

    Clock Tuning
    29.
    发明申请
    Clock Tuning 审中-公开

    公开(公告)号:US20190258288A1

    公开(公告)日:2019-08-22

    申请号:US15901597

    申请日:2018-02-21

    Applicant: NXP B.V.

    Abstract: Aspects of the present disclosure involving tuning clock signal sources for communication. As may be implemented in accordance with one or more embodiments, trustworthiness of a message or a source of the message is validated, as indicated by data received over a data bus that communicatively couples a plurality of circuits respectively including an independent clock signal source. Data sent between the circuits can be received by adaptively sampling data that is carried by the data bus. Timing information is calculated relative to data frames of the data received over the data bus, and a clock signal source at one of the circuits is tuned in response to the validating and the calculating.

    Controller area network (CAN) device and method for controlling CAN traffic

    公开(公告)号:US10361934B2

    公开(公告)日:2019-07-23

    申请号:US14868223

    申请日:2015-09-28

    Applicant: NXP B.V.

    Abstract: Embodiments of a device and method are disclosed. A controller area network (CAN) device includes a compare module configured to interface with a CAN transceiver, the compare module having a receive data (RXD) interface configured to receive data from the CAN transceiver, a CAN decoder configured to decode an identifier of a CAN message received from the RXD interface, and an identifier memory configured to store an entry that corresponds to at least one identifier, and compare logic configured to compare a received identifier from a CAN message to the entry that is stored in the identifier memory and to output a match signal when the comparison indicates that the received identifier of the CAN message matches the entry that is stored at the CAN device. The CAN device also includes a signal generator configured to output, in response to the match signal, a signal to invalidate the CAN message.

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