Versatile system for limiting electric field degradation of semiconductor structures
    21.
    发明授权
    Versatile system for limiting electric field degradation of semiconductor structures 有权
    用于限制半导体结构电场退化的通用系统

    公开(公告)号:US07101751B2

    公开(公告)日:2006-09-05

    申请号:US10850751

    申请日:2004-05-21

    IPC分类号: H01L29/72

    摘要: The present invention provides a system for limiting degradation of a first semiconductor structure (304) caused by an electric field (314), generated from within the semiconductor substrate (302) by high voltage on a second semiconductor structure (310). A semiconductor device (300) is adapted to reduce the effective magnitude of the field—as realized at structure 304—to some fractional component (320), or to render the angle (322)—at which the field approaches the first structure through a first substrate region (306)—acute. Certain embodiments of the present invention provide for: lateral recession of the first semiconductor structure to abut an isolation structure (312), which is disposed between the second semiconductor structure and the first substrate region; lateral recession of the first semiconductor structure from the isolation structure, so as to form a moat therebetween; and a counter-doped region (316) within the first substrate region.

    摘要翻译: 本发明提供了一种用于限制由在第二半导体结构(310)上由高电压从半导体衬底(302)内部产生的电场(314)引起的第一半导体结构(304)劣化的系统。 半导体器件(300)适于将场结构304的有效幅度减小到一些分数分量(320),或者使得该场接近第一结构的角度(322) 第一衬底区域(306) - 突出。 本发明的某些实施例提供:第一半导体结构的侧向凹陷以邻接设置在第二半导体结构和第一基底区域之间的隔离结构(312); 所述第一半导体结构从所述隔离结构侧向退缩,以在其间形成护城河; 和在第一衬底区域内的反掺杂区域(316)。

    Method of providing polysilicon spacer for implantation

    公开(公告)号:US06573165B2

    公开(公告)日:2003-06-03

    申请号:US10184520

    申请日:2002-06-28

    申请人: PR Chidambaram

    发明人: PR Chidambaram

    IPC分类号: H01L21425

    摘要: An improved method of implanting source and drain for CMOS devices is provided by a hard mask and dry etching to form polysilicon gates 20 percent longer than desired, implanting to form the source and drain of the PMOS transistor with dopant that moves faster during annealing such as Boron and then wet etching the polysilicon gates down to the shorter length such as the final length before implanting with the faster dopant such as arsenic.