Cutlery utensil dispensing apparatus and method
    23.
    发明授权
    Cutlery utensil dispensing apparatus and method 有权
    餐具用具分配装置及方法

    公开(公告)号:US08070013B2

    公开(公告)日:2011-12-06

    申请号:US12349203

    申请日:2009-01-06

    IPC分类号: A47F1/10

    CPC分类号: A47F1/10 A47F2001/103

    摘要: A cutlery utensil dispenser has a dispensing tray with a floor and a region housing a cutlery utensil. The cutlery utensil has first and second portions and is moved by an engagement portion of an actuator from a first orientation to a second orientation. In the first orientation, the cutlery utensil rests on the floor in the region and is within the cutlery utensil dispenser, inaccessible to a user. In the second orientation, the second portion of the cutlery utensil projects from the cutlery utensil dispenser and is accessible to the user. A wall of the region has a fulcrum end dimensioned to engage the cutlery utensil. The cutlery utensil rotates about the fulcrum end responsive to the engagement portion toward an exit of the dispenser.

    摘要翻译: 餐具用具分配器具有带有地板的分配托盘和容纳餐具的区域。 餐具具有第一和第二部分,并且通过致动器的接合部分从第一取向移动到第二取向。 在第一方向上,餐具放置在该区域的地板上并且在餐具用具分配器内,用户不可访问。 在第二方向上,餐具的第二部分从餐具用具分配器突出并且可由用户访问。 该区域的壁具有支点端,其尺寸适于接合餐具。 餐具餐具响应于接合部分朝向分配器的出口而围绕支点端旋转。

    Processing Seismic Data Using Combined Regularization and 4D Binning
    25.
    发明申请
    Processing Seismic Data Using Combined Regularization and 4D Binning 有权
    使用组合正则化和4D分选处理地震数据

    公开(公告)号:US20090290449A1

    公开(公告)日:2009-11-26

    申请号:US12126892

    申请日:2008-05-25

    IPC分类号: G01V1/28

    CPC分类号: G01V1/28 G01V2210/57

    摘要: To process seismic data, a combined four-dimensional (4D) binning and regularization procedure is performed on the seismic data, where the combined 4D binning and regularization procedure includes computing measures associated with regularization of the seismic data, computing measures associated with 4D binning, and processing the seismic data according to the regularization measures and 4D binning measures.

    摘要翻译: 为了处理地震数据,对地震数据进行组合的四维(4D)合并和正则化程序,其中组合的4D合并和正则化程序包括与地震数据的正规化相关的计算措施,与4D合并相关联的计算措施, 并根据正规化措施和4D合并措施处理地震数据。

    Multi-channel buffered serial port debugging

    公开(公告)号:US07028118B2

    公开(公告)日:2006-04-11

    申请号:US10256504

    申请日:2002-09-27

    IPC分类号: G06F13/36

    CPC分类号: G06F13/376

    摘要: In digital signal processors serial data is passed in out and of the chip in a time division multiplexed (TDM) fashion. The TDM stream consists of many independent channels of serial data. The complexity of generating interleaved TDM serial data from multiple sources particularly in the case of multi-processor systems. This process is normally driven by a program resident on each processor. The proper sequencing of the TDM serial stream must be tested prior to making the multi-processor device ready for its application. This invention describes the use of minimal added hardware and a single output pin allowing the test and debug of program errors or device malfunctions in output serial data.

    Link order replacement optimization

    公开(公告)号:US06999423B2

    公开(公告)日:2006-02-14

    申请号:US09995219

    申请日:2001-11-27

    IPC分类号: H04L12/26

    CPC分类号: H04W24/02 H04W24/00

    摘要: A method and system for optimizing a mobile radio network topology for an N node network where each node has K connecting links. A base network topology is established and a cost value is determined for the base network. It is determined if all possible local transformations on the base network topology have been performed and if not a local transformation is performed on the base network to form a transformed network. A cost is calculated for the transformed network and the cost is compared with the cost of a base network. The transformed network is established as the base network if the cost of the transformed network is less than the cost of the base network.

    Channelized delay and mix chip rate detector
    30.
    发明授权
    Channelized delay and mix chip rate detector 失效
    信道化延迟和混合码片率检测器

    公开(公告)号:US5063572A

    公开(公告)日:1991-11-05

    申请号:US533183

    申请日:1990-06-04

    IPC分类号: H04B1/692 H04K3/00

    CPC分类号: H04B1/692 H04K3/228

    摘要: A detector circuit for indicating the chip rate of a direct sequence frequency hopped data transmission signal. The wide band input signal is channelized into L adjacent sub-bands and each sub-band signal is multiplied by a delayed copy of itself and then hard limited, after which all the hard limited product signals are totalized to give a resultant signal representative of the chip rate.

    摘要翻译: 一种用于指示直接序列跳频数据传输信号的码片速率的检测器电路。 宽带输入信号被信道化为L个相邻子带,并且每个子带信号乘以其自身的延迟拷贝,然后硬限制,之后将所有硬限制乘积信号进行累加,得到代表 芯片速率。