利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

52 条记录 (耗时 0.025 秒)

    Cutlery utensil dispensing apparatus and method
    1.
    发明授权
    Cutlery utensil dispensing apparatus and method 有权
    餐具用具分配装置及方法

    公开(公告)号：US08070013B2

    公开(公告)日：2011-12-06

    申请号：US12349203

    申请日：2009-01-06

    申请人： Christopher M. Reinsel ,  Patrick J. Smith

    发明人： Christopher M. Reinsel ,  Patrick J. Smith

    IPC分类号： A47F1/10

    CPC分类号： A47F1/10 ,  A47F2001/103

    摘要： A cutlery utensil dispenser has a dispensing tray with a floor and a region housing a cutlery utensil. The cutlery utensil has first and second portions and is moved by an engagement portion of an actuator from a first orientation to a second orientation. In the first orientation, the cutlery utensil rests on the floor in the region and is within the cutlery utensil dispenser, inaccessible to a user. In the second orientation, the second portion of the cutlery utensil projects from the cutlery utensil dispenser and is accessible to the user. A wall of the region has a fulcrum end dimensioned to engage the cutlery utensil. The cutlery utensil rotates about the fulcrum end responsive to the engagement portion toward an exit of the dispenser.

    摘要翻译： 餐具用具分配器具有带有地板的分配托盘和容纳餐具的区域。 餐具具有第一和第二部分，并且通过致动器的接合部分从第一取向移动到第二取向。 在第一方向上，餐具放置在该区域的地板上并且在餐具用具分配器内，用户不可访问。 在第二方向上，餐具的第二部分从餐具用具分配器突出并且可由用户访问。 该区域的壁具有支点端，其尺寸适于接合餐具。 餐具餐具响应于接合部分朝向分配器的出口而围绕支点端旋转。

    CUTLERY UTENSIL DISPENSING APPARATUS AND METHOD
    2.
    发明申请
    CUTLERY UTENSIL DISPENSING APPARATUS AND METHOD 有权
    CUTLERY UTENSIL分配装置和方法

    公开(公告)号：US20100170915A1

    公开(公告)日：2010-07-08

    申请号：US12349203

    申请日：2009-01-06

    申请人： Christopher M. Reinsel ,  Patrick J. Smith

    发明人： Christopher M. Reinsel ,  Patrick J. Smith

    IPC分类号： B65D83/00

    CPC分类号： A47F1/10 ,  A47F2001/103

    摘要： A cutlery utensil dispenser has a dispensing tray with a floor and a region housing a cutlery utensil. The cutlery utensil has first and second portions and is moved by an engagement portion of an actuator from a first orientation to a second orientation. In the first orientation, the cutlery utensil rests on the floor in the region and is within the cutlery utensil dispenser, inaccessible to a user. In the second orientation, the second portion of the cutlery utensil projects from the cutlery utensil dispenser and is accessible to the user. A wall of the region has a fulcrum end dimensioned to engage the cutlery utensil. The cutlery utensil rotates about the fulcrum end responsive to the engagement portion toward an exit of the dispenser.

    摘要翻译： 餐具用具分配器具有带有地板的分配托盘和容纳餐具的区域。 餐具具有第一和第二部分，并且通过致动器的接合部分从第一取向移动到第二取向。 在第一方向上，餐具放置在该区域的地板上并且在餐具用具分配器内，用户不可访问。 在第二方向上，餐具的第二部分从餐具用具分配器突出并且可由用户访问。 该区域的壁具有支点端，其尺寸适于接合餐具。 餐具餐具响应于接合部分朝向分配器的出口而围绕支点端旋转。

    Multicore DSP device having coupled subsystem memory buses for global DMA access
    4.
    发明授权
    Multicore DSP device having coupled subsystem memory buses for global DMA access 有权
    具有用于全局DMA访问的耦合子系统存储器总线的多核DSP设备

    公开(公告)号：US06892266B2

    公开(公告)日：2005-05-10

    申请号：US10008696

    申请日：2001-11-08

    申请人： Jay B. Reimer ,  Harland Glenn Hopkins ,  Tai H. Nguyen ,  Yi Luo ,  Kevin A. McGonagle ,  Jason A. Jones ,  Duy Q. Nguyen ,  Patrick J. Smith

    发明人： Jay B. Reimer ,  Harland Glenn Hopkins ,  Tai H. Nguyen ,  Yi Luo ,  Kevin A. McGonagle ,  Jason A. Jones ,  Duy Q. Nguyen ,  Patrick J. Smith

    IPC分类号： G06F9/30 ,  G06F13/16 ,  G06F13/28 ,  G06F13/362 ,  G06F15/78 ,  G06F13/14

    CPC分类号： G06F13/28

    摘要： A DSP device is disclosed having multiple DMA controllers with global DMA access to all volatile memory resources in the DSP device. In a preferred embodiment, each of the DMA controllers is coupled to each of the memory buses and is configured to control each of the memory buses. A memory bus multiplexer may be coupled between the subsystem memory bus and each of the DMA controllers, and an arbiter may be used to set the memory bus multiplexer so as to allow any one of the DMA controllers to control the memory bus. The memory bus may also be controlled by the host port interface via the memory bus multiplexer. A round-robin arbitration technique is used to provide each of the controllers and the host port interface fair access to the memory bus. This approach may advantageously provide increased flexibility in the use of DMA controllers to transfer data from place to place, with only a minimal increase in complexity.

    摘要翻译： 公开了具有多个DMA控制器的DSP设备，其全局DMA访问DSP设备中的所有易失性存储器资源。 在优选实施例中，每个DMA控制器耦合到每个存储器总线，并且被配置为控制每个存储器总线。 存储器总线多路复用器可以耦合在子系统存储器总线和每个DMA控制器之间，并且仲裁器可以用于设置存储器总线多路复用器，以便允许任何一个DMA控制器来控制存储器总线。 存储器总线也可以经由存储器总线多路复用器由主机端口接口来控制。 循环仲裁技术用于提供每个控制器和主机端口接口公平地访问存储器总线。 这种方法可以有利地提供使用DMA控制器将数据从一个地方传输到另一个地方的增加的灵活性，只有最小的复杂性增加。

    Apparatus and method for activation of a digital signal processor in an idle mode for interprocessor transfer of signal groups in a digital signal processing unit
    5.
    发明授权
    Apparatus and method for activation of a digital signal processor in an idle mode for interprocessor transfer of signal groups in a digital signal processing unit 有权
    用于在空闲模式下激活数字信号处理器的装置和方法，用于数字信号处理单元中的信号组的处理器间传送

    公开(公告)号：US06789183B1

    公开(公告)日：2004-09-07

    申请号：US09670664

    申请日：2000-09-27

    申请人： Patrick J. Smith ,  Jason A. Jones ,  Kevin A. McGonagle

    发明人： Patrick J. Smith ,  Jason A. Jones ,  Kevin A. McGonagle

    IPC分类号： G06F1328

    CPC分类号： G06F13/28 ,  Y02D10/14

    摘要： In a digital processing unit having a plurality of digital signal processors, a first digital signal processor can request a direct transfer of a signal group stored in the memory unit of a second digital signal processor. In order to insure that the second digital signal is active, a control signal is generated by the direct memory access controller of the first digital signal processor. The control signal is applied the directly to the memory access controller of the second digital signal processor. When the second digital signal processor is in an IDLE mode, the control signal activates the second digital signal processor.

    摘要翻译： 在具有多个数字信号处理器的数字处理单元中，第一数字信号处理器可以请求存储在第二数字信号处理器的存储单元中的信号组的直接传送。 为了确保第二数字信号有效，控制信号由第一数字信号处理器的直接存储器存取控制器产生。 控制信号被直接施加到第二数字信号处理器的存储器存取控制器。 当第二数字信号处理器处于空闲模式时，控制信号激活第二数字信号处理器。

    Channelized binary-level radiometer
    6.
    发明授权
    Channelized binary-level radiometer 失效
    信道化二进制级辐射计

    公开(公告)号：US4956644A

    公开(公告)日：1990-09-11

    申请号：US417124

    申请日：1989-10-04

    申请人： Ronald S. Leahy ,  Patrick J. Smith ,  Scott R. Bullock

    发明人： Ronald S. Leahy ,  Patrick J. Smith ,  Scott R. Bullock

    IPC分类号： H04B1/713 ,  H04B1/715

    CPC分类号： H04B1/715 ,  H04B1/713 ,  H04B2001/7152

    摘要： A signal detector for receiving a wide band (W) of frequency-hopped signals which channelizes the incoming signals, via filter banks into a plurality (L) of channels. Magnitude squaring circuits in each channel generate a "power" estimate which is compared to a preset threshold value by threshold-quantizer units that produce a positive voltage (=1) if the threshold is exceeded. After summation of all the channels, the direct sequence (DS) signal component and noise component are processed so that a DC voltage is produced if a frequency-hop signal (FH) is present which is greater in value than when the signal is not present. Thus the DC signal indicates whether the FH signal is present or absent.

    摘要翻译： 一种信号检测器，用于接收频带跳频信号的宽带（W），其将输入信号通过滤波器组分频成多个（L）个信道。 每个通道中的幅度平方电路产生“功率”估计，其通过产生正电压（= 1）的阈值量化器单元与预设阈值进行比较，如果超过阈值。 在所有通道的总和之后，处理直接序列（DS）信号分量和噪声分量，使得如果存在与不存在信号时相比值大的频率跳跃信号（FH），则产生直流电压 。 因此，DC信号指示FH信号是存在还是不存在。

    Narrowband parameter estimator
    7.
    发明授权
    Narrowband parameter estimator 失效
    窄带参数估计器

    公开(公告)号：US4947361A

    公开(公告)日：1990-08-07

    申请号：US250795

    申请日：1988-09-28

    申请人： Patrick J. Smith ,  Scott R. Bullock ,  Jeffery Mac Thornock

    发明人： Patrick J. Smith ,  Scott R. Bullock ,  Jeffery Mac Thornock

    IPC分类号： H03H21/00

    CPC分类号： H03H21/0012

    摘要： A narrowband parameter estimator circuit is described which can be used to estimate the frequency and the relative power of narrowband interference tones which reside in a wideband information signal. A two-weight adaptive filter with a phase/frequency-lock loop circuit works in conjunction with a stepped synthesizer to lock onto the individual narrowband interference tones. A lock-detect circuit signals a digital logic unit to record the frequency of the stepped synthesizer and to measure the power in the adaptive filter output signal. This same output signal is used to cancel the unwanted tone in the wideband information signal being transmitted.

    摘要翻译： 描述了可以用于估计位于宽带信息信号中的窄带干扰音调的频率和相对功率的窄带参数估计器电路。 具有相位/频率锁定环路电路的双重自适应滤波器与阶梯式合成器一起工作，以锁定到各个窄带干扰音调上。 锁定检测电路向数字逻辑单元发出信号以记录阶梯式合成器的频率并测量自适应滤波器输出信号中的功率。 该相同的输出信号用于消除所发送的宽带信息信号中的不需要的音调。

    Method and apparatus for processing data in an embedded system
    9.
    发明授权
    Method and apparatus for processing data in an embedded system 有权
    用于在嵌入式系统中处理数据的方法和装置

    公开(公告)号：US08667254B1

    公开(公告)日：2014-03-04

    申请号：US12121614

    申请日：2008-05-15

    申请人： Carl F. Rohrer ,  Patrick J. Smith ,  Stacey Secatch

    发明人： Carl F. Rohrer ,  Patrick J. Smith ,  Stacey Secatch

    IPC分类号： G06F15/163 ,  G06F15/80

    CPC分类号： G06F15/167

    摘要： In one embodiment, a network device is disclosed. For example, in one embodiment of the present invention, the device comprises a processor and a core memory having a receive buffer and a transmit buffer. The device comprises a bus coupled to the processor and the core memory. The device comprises at least one co-processor coupled to the core memory via a direct link, wherein the at least one co-processor is capable of accessing at least one of: the receive buffer, or the transmit buffer, without assistance from the processor.

    摘要翻译： 在一个实施例中，公开了一种网络设备。 例如，在本发明的一个实施例中，该设备包括处理器和具有接收缓冲器和发送缓冲器的核心存储器。 该设备包括耦合到处理器和核心存储器的总线。 该设备包括经由直接链路耦合到核心存储器的至少一个协处理器，其中所述至少一个协处理器能够在没有来自处理器的协助下访问以下中的至少一个：接收缓冲器或发送缓冲器 。