SYSTEMS AND METHODS FOR CACHE LINE REPLACEMENT
    21.
    发明申请
    SYSTEMS AND METHODS FOR CACHE LINE REPLACEMENT 有权
    用于高速缓存行替换的系统和方法

    公开(公告)号:US20130254489A1

    公开(公告)日:2013-09-26

    申请号:US13894545

    申请日:2013-05-15

    CPC classification number: G06F12/0808 G06F12/121 G06F2212/1016 Y02D10/13

    Abstract: A computer readable storage medium includes instructions that, when executed by a processor, cause the processor to receive an index value included in a cache invalidate by index instruction, an encoded way value, and an incrementer output value. The instructions further cause the processor to assign the index value as an identifier value in response to receiving the cache invalidate by index instruction. The identifier value indicates a cache line for replacement.

    Abstract translation: 计算机可读存储介质包括当由处理器执行时使处理器通过索引指令,编码方式值和递增器输出值来接收包括在高速缓存无效中的索引值的指令。 指令进一步导致处理器响应于通过索引指令接收到高速缓存无效而将索引值分配为标识符值。 标识符值表示用于替换的高速缓存行。

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