利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

21 条记录 (耗时 0.015 秒)

    USING THE LEAST SIGNIFICANT BITS OF A CALLED FUNCTION'S ADDRESS TO SWITCH PROCESSOR MODES
    2.
    发明申请
    USING THE LEAST SIGNIFICANT BITS OF A CALLED FUNCTION'S ADDRESS TO SWITCH PROCESSOR MODES 审中-公开
    使用呼叫功能地址的最小重要位置切换处理器模式

    公开(公告)号：US20130205115A1

    公开(公告)日：2013-08-08

    申请号：US13655499

    申请日：2012-10-19

    申请人： QUALCOMM INCORPORATED

    发明人： Charles Joseph Tabony ,  Erich James Plondke ,  Lucian Codrescu ,  Suresh K. Venkumahanti ,  Evandro Carlos Menezes

    IPC分类号： G06F9/30 ,  G06F9/315

    CPC分类号： G06F9/30189 ,  G06F9/30054 ,  G06F9/30076 ,  G06F9/30149 ,  G06F9/30181 ,  G06F9/322 ,  G06F9/3816

    摘要： Systems and methods for tracking and switching between execution modes in processing systems. A processing system is configured to execute instructions in at least two instruction execution triodes including a first and second execution mode chosen from a classic/aligned mode and a compressed/unaligned mode. Target addresses of selected instructions such as calls and returns are forcibly misaligned in the compressed mode, such one or more bits, such as, the least significant bits (alignment bits) of the target address in the compressed mode are different from the corresponding alignment bits in the classic mode. When the selected instructions are encountered during execution in the first mode, a decision to switch operation to the second mode is based on analyzing the alignment bits of the target address of the selected instruction.

    摘要翻译： 在处理系统中跟踪和切换执行模式的系统和方法。 处理系统被配置为在至少两个指令执行三极管中执行指令，包括从经典/对准模式和压缩/未对准模式选择的第一和第二执行模式。 所选择的指令（例如呼叫和返回）的目标地址在压缩模式下被强制地未对准，诸如压缩模式中的目标地址的最低有效位（对齐比特）之类的一个或多个比特与对应的比对比特不同 在经典模式下。 当在第一模式中执行期间遇到所选择的指令时，将操作切换到第二模式的决定是基于分析所选指令的目标地址的对准比特。

    Hardware-based stack control information protection
    4.
    发明授权
    Hardware-based stack control information protection 有权
    基于硬件的堆栈控制信息保护

    公开(公告)号：US09390264B2

    公开(公告)日：2016-07-12

    申请号：US14256681

    申请日：2014-04-18

    申请人： QUALCOMM Incorporated

    发明人： Can Erkin Acar ,  Erich James Plondke ,  Robert J. Turner ,  Billy B. Brumley

    IPC分类号： G06F21/56 ,  G06F21/54 ,  G06F21/52

    CPC分类号： G06F21/56 ,  G06F21/52 ,  G06F21/54

    摘要： Techniques for protecting contents of a stack associated with a processor are provided. The techniques include a method including receiving a store instruction from a software program being executed by the processor, the store instruction including control information associated with a subroutine, altering the control information to generate secured control information responsive to receiving the store instruction from the software program, storing the secured control information on the stack, receiving a load instruction from the software program; and responsive to receiving the load instruction from the software program, loading the secured control information from the stack, altering the secured control information to recover the control information, and returning the control information to the software program.

    摘要翻译： 提供了用于保护与处理器相关联的堆栈的内容的技术。 这些技术包括一种方法，包括从由处理器执行的软件程序接收存储指令，存储指令包括与子程序相关的控制信息，改变控制信息以产生响应于从软件程序接收存储指令的安全控制信息 将所述安全控制信息存储在所述堆栈上，从所述软件程序接收加载指令; 并且响应于从所述软件程序接收到所述加载指令，从所述堆栈加载所述安全控制信息，改变所述安全控制信息以恢复所述控制信息，以及将所述控制信息返回给所述软件程序。

    Dedicated arithmetic encoding instruction
    8.
    发明授权
    Dedicated arithmetic encoding instruction 有权
    专用算术编码指令

    公开(公告)号：US09455743B2

    公开(公告)日：2016-09-27

    申请号：US14288018

    申请日：2014-05-27

    申请人： QUALCOMM Incorporated

    发明人： Bo Zhou ,  Mao Zeng ,  Erich James Plondke ,  Lucian Codrescu ,  Shu Xiao ,  Junchen Du ,  Suhail Jalil

    IPC分类号： H03M7/00 ,  H03M7/40 ,  G06F9/30 ,  G06F9/38 ,  H04N19/91 ,  H04N19/13

    CPC分类号： H03M7/4018 ,  G06F9/30018 ,  G06F9/30025 ,  G06F9/3895 ,  H04N19/13 ,  H04N19/42 ,  H04N19/91

    摘要： A method includes executing, at a processor, a dedicated arithmetic encoding instruction. The dedicated arithmetic encoding instruction accepts a plurality of inputs including a first range, a first offset, and a first state and produces one or more outputs based on the plurality of inputs. The method also includes storing a second state, realigning the first range to produce a second range, and realigning the first offset to produce a second offset based on the one or more outputs of the dedicated arithmetic encoding instruction.

    摘要翻译： 一种方法包括在处理器处执行专用算术编码指令。 专用算术编码指令接受包括第一范围，第一偏移和第一状态的多个输入，并且基于多个输入产生一个或多个输出。 该方法还包括存储第二状态，重新对准第一范围以产生第二范围，以及基于专用算术编码指令的一个或多个输出来重新对准第一偏移以产生第二偏移。