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    Register files for a digital signal processor operating in an interleaved multi-threaded environment
    2.
    发明授权
    Register files for a digital signal processor operating in an interleaved multi-threaded environment 有权
    为交错多线程环境中的数字信号处理器注册文件

    公开(公告)号：US09235418B2

    公开(公告)日：2016-01-12

    申请号：US14189313

    申请日：2014-02-25

    Applicant: QUALCOMM Incorporated

    Inventor： Muhammad Ahmed ,  Erich James Plondke ,  Lucian Codrescu ,  William C. Anderson

    IPC: G06F15/76 ,  G06F9/30 ,  G06F7/38 ,  G06F13/00 ,  G06F9/38

    CPC classification number: G06F9/30149 ,  G06F9/3012 ,  G06F9/3851 ,  G06F9/3885

    Abstract: A processor device includes a memory and a sequencer that is responsive to the memory. The sequencer supports very long instruction word (VLIW) type instructions and at least one VLIW instruction packet uses a number of operands during execution, The processor device further includes a plurality of instruction execution units responsive to the sequencer and a plurality of register files. Each of the plurality of register files includes a plurality of registers and the plurality of register files are coupled to the plurality of instruction execution units. Further, each of the plurality of register flies includes a number of data read ports and the number of data read ports of each of the plurality of register files is less than the number of operands used by the at least one VLIW instruction packet.

    Abstract translation: 处理器设备包括响应于存储器的存储器和定序器。 定序器支持非常长的指令字（VLIW）类型指令，并且至少一个VLIW指令分组在执行期间使用多个操作数。处理器设备还包括响应于定序器的多个指令执行单元和多个寄存器文件。 多个寄存器文件中的每一个包括多个寄存器，并且多个寄存器文件耦合到多个指令执行单元。 此外，多个寄存器苍蝇中的每一个包括多个数据读取端口，并且多个寄存器文件中的每一个的数据读取端口的数量小于由至少一个VLIW指令包使用的操作数的数量。

    DEDICATED ARITHMETIC ENCODING INSTRUCTION
    3.
    发明申请
    DEDICATED ARITHMETIC ENCODING INSTRUCTION 有权
    专用算术编码指令

    公开(公告)号：US20150349796A1

    公开(公告)日：2015-12-03

    申请号：US14288018

    申请日：2014-05-27

    Applicant: QUALCOMM Incorporated

    Inventor： Bo Zhou ,  Mao Zeng ,  Erich James Plondke ,  Lucian Codrescu ,  Shu Xiao ,  Junchen Du ,  Suhail Jalil

    IPC: H03M7/40

    CPC classification number: H03M7/4018 ,  G06F9/30018 ,  G06F9/30025 ,  G06F9/3895 ,  H04N19/13 ,  H04N19/42 ,  H04N19/91

    Abstract: A method includes executing, at a processor, a dedicated arithmetic encoding instruction. The dedicated arithmetic encoding instruction accepts a plurality of inputs including a first range, a first offset, and a first state and produces one or more outputs based on the plurality of inputs. The method also includes storing a second state, realigning the first range to produce a second range, and realigning the first offset to produce a second offset based on the one or more outputs of the dedicated arithmetic encoding instruction.

    Abstract translation: 一种方法包括在处理器处执行专用算术编码指令。 专用算术编码指令接受包括第一范围，第一偏移和第一状态的多个输入，并且基于多个输入产生一个或多个输出。 该方法还包括存储第二状态，重新对准第一范围以产生第二范围，以及基于专用算术编码指令的一个或多个输出来重新对准第一偏移以产生第二偏移。

    CONFIGURABLE TRANSLATION LOOKASIDE BUFFER
    4.
    发明申请
    CONFIGURABLE TRANSLATION LOOKASIDE BUFFER 审中-公开
    可配置翻译LOOKASIDE BUFFER

    公开(公告)号：US20140068225A1

    公开(公告)日：2014-03-06

    申请号：US14073190

    申请日：2013-11-06

    Applicant: QUALCOMM Incorporated

    Inventor： Erich James Plondke ,  Ajay Anant Ingle ,  Lucian Codrescu ,  Paul D. Bassett

    IPC: G06F12/10

    CPC classification number: G06F12/1027 ,  G06F2212/1028 ,  Y02D10/13

    Abstract: A particular method includes receiving at least one translation lookaside buffer (TLB) configuration indicator. The at least one TLB configuration indicator indicates a specific number of entries to be enabled at a TLB. The method further includes modifying a number of searchable entries of the TLB in response to the at least one TLB configuration indicator.

    Abstract translation: 一种特定的方法包括接收至少一个翻译后备缓冲器（TLB）配置指示符。 至少一个TLB配置指示符指示将在TLB处启用的特定数量的条目。 所述方法还包括响应于所述至少一个TLB配置指示符来修改所述TLB的可搜索条目的数量。

    Methods and apparatus for storage and translation of entropy encoded software embedded within a memory hierarchy
    5.
    发明授权
    Methods and apparatus for storage and translation of entropy encoded software embedded within a memory hierarchy 有权

    公开(公告)号：US10754653B2

    公开(公告)日：2020-08-25

    申请号：US14950612

    申请日：2015-11-24

    Applicant: QUALCOMM Incorporated

    Inventor： Sergei Larin ,  Lucian Codrescu ,  Anshuman Das Gupta

    IPC: G06F12/00 ,  G06F9/30

    Abstract: A system for translating compressed instructions to instructions in an executable format is described. A translation unit is configured to decompress compressed instructions into a native instruction format using X and Y indices accessed from a memory, a translation memory, and a program specified mix mask. A level 1 cache is configured to store the native instruction format for each compressed instruction. The memory may be configured as a paged instruction cache to store pages of compressed instructions intermixed with pages of uncompressed instructions. Methods of determining a mix mask for efficiently translating compressed instructions is also described. A genetic method uses pairs of mix masks as genes from a seed population of mix masks that are bred and may be mutated to produce pairs of offspring mix masks to update the seed population. A mix mask for efficiently translating compressed instructions is determined from the updated seed population.

    Instruction cache having a multi-bit way prediction mask
    10.
    发明授权
    Instruction cache having a multi-bit way prediction mask 有权
    具有多位方式预测掩码的指令高速缓存

    公开(公告)号：US09304932B2

    公开(公告)日：2016-04-05

    申请号：US13721317

    申请日：2012-12-20

    Applicant: QUALCOMM Incorporated

    Inventor： Peter G. Sassone ,  Suresh K. Venkumahanti ,  Lucian Codrescu

    IPC: G06F12/00 ,  G06F12/08 ,  G06F9/38

    CPC classification number: G06F12/0875 ,  G06F9/3802 ,  G06F9/3806 ,  G06F9/3832 ,  G06F12/0864 ,  G06F2212/6082 ,  Y02D10/13

    Abstract: In a particular embodiment, an apparatus includes control logic configured to selectively set bits of a multi-bit way prediction mask based on a prediction mask value. The control logic is associated with an instruction cache including a data array. A subset of line drivers of the data array is enabled responsive to the multi-bit way prediction mask. The subset of line drivers includes multiple line drivers.

    Abstract translation: 在特定实施例中，一种装置包括配置成基于预测掩模值有选择地设置多位方式预测掩模的比特的控制逻辑。 控制逻辑与包括数据阵列的指令高速缓存相关联。 数据阵列的线路驱动器的一个子集是响应于多位方式预测掩码启用的。 线路驱动器的子集包括多个线路驱动器。

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