公开(公告)号：US08473439B2

公开(公告)日：2013-06-25

申请号：US12963558

申请日：2010-12-08

申请人： John V. Arthur ,  Gregory S. Corrado ,  Steven K. Esser ,  Paul A. Merolla ,  Dharmendra S. Modha

发明人： John V. Arthur ,  Gregory S. Corrado ,  Steven K. Esser ,  Paul A. Merolla ,  Dharmendra S. Modha

IPC分类号： G06N5/00

CPC分类号： G06N3/049

摘要： An integrate and fire electronic neuron is disclosed. Upon receiving an external spike signal, a digital membrane potential of the electronic neuron is updated based on the external spike signal. The electric potential of the membrane is decayed based on a leak rate. Upon the electric potential of the membrane exceeding a threshold, a spike signal is generated.

摘要翻译： 公开了一种整合和消防电子神经元。 在接收到外部尖峰信号时，基于外部尖峰信号更新电子神经元的数字膜电位。 膜的电位根据泄漏率衰减。 当膜的电位超过阈值时，产生尖峰信号。

公开(公告)号：US09524462B2

公开(公告)日：2016-12-20

申请号：US13598915

申请日：2012-08-30

申请人： Steven K. Esser ,  Dharmendra S. Modha ,  Anthony Ndirango

发明人： Steven K. Esser ,  Dharmendra S. Modha ,  Anthony Ndirango

IPC分类号： G06F15/18 ,  G06N3/08 ,  G06N3/04 ,  G06N3/063

CPC分类号： G06N3/049 ,  G06N3/063 ,  G06N3/08

摘要： Embodiments of the invention relate to canonical spiking neurons for spatiotemporal associative memory. An aspect of the invention provides a spatiotemporal associative memory including a plurality of electronic neurons having a layered neural net relationship with directional synaptic connectivity. The plurality of electronic neurons configured to detect the presence of a spatiotemporal pattern in a real-time data stream, and extract the spatiotemporal pattern. The plurality of electronic neurons are further configured to, based on learning rules, store the spatiotemporal pattern in the plurality of electronic neurons, and upon being presented with a version of the spatiotemporal pattern, retrieve the stored spatiotemporal pattern.

摘要翻译： 本发明的实施例涉及用于时空关联记忆的规范加标神经元。 本发明的一个方面提供了包括具有与定向突触连通性的分层神经网络关系的多个电子神经元的时空相关存储器。 多个电子神经元被配置为检测实时数据流中的时空模式的存在，并提取时空模式。 多个电子神经元还被配置为基于学习规则将时空图案存储在多个电子神经元中，并且在呈现时空图案的版本时，检索存储的时空图案。

公开(公告)号：US20140032464A1

公开(公告)日：2014-01-30

申请号：US13434733

申请日：2012-03-29

申请人： Steven K. Esser ,  Dharmendra S. Modha

发明人： Steven K. Esser ,  Dharmendra S. Modha

IPC分类号： G06N3/063

CPC分类号： G06N3/04 ,  G06F9/44505 ,  G06N3/049 ,  G06N3/063 ,  G06N3/088

摘要： Embodiments of the invention provide a neural core circuit comprising a synaptic interconnect network including plural electronic synapses for interconnecting one or more source electronic neurons with one or more target electronic neurons. The interconnect network further includes multiple axon paths and multiple dendrite paths. Each synapse is at a cross-point junction of the interconnect network between a dendrite path and an axon path. The core circuit further comprises a routing module maintaining routing information. The routing module routes output from a source electronic neuron to one or more selected axon paths. Each synapse provides a configurable level of signal conduction from an axon path of a source electronic neuron to a dendrite path of a target electronic neuron.

摘要翻译： 本发明的实施例提供了一种包括突触互连网络的神经核心电路，其包括用于将一个或多个源电子神经元与一个或多个目标电子神经元相互连接的多个电子突触。 互连网络还包括多个轴突路径和多个树枝状路径。 每个突触处于互连网络在树枝状路径和轴突路径之间的交叉点处。 核心电路还包括维护路由信息的路由模块。 路由模块将源电子神经元的输出路由到一个或多个选择的轴突路径。 每个突触提供从源电子神经元的轴突路径到目标电子神经元的枝晶路径的可配置水平的信号传导。

公开(公告)号：US20130198121A1

公开(公告)日：2013-08-01

申请号：US13360622

申请日：2012-01-27

申请人： Dharmendra S. Modha ,  Steven K. Esser

发明人： Dharmendra S. Modha ,  Steven K. Esser

IPC分类号： G06N3/04

CPC分类号： G06N3/063 ,  G06N3/049

摘要： Embodiments of the present invention provide a neural module comprising a multilevel hierarchical structure of neural compartments. Each neural compartment is interconnected to one or more neural compartments of a previous level and a next hierarchical level in the hierarchical structure. Each neural compartment integrates spike signals from interconnected neural compartments of a previous hierarchical level, generates a spike signal in response to the integrated spike signals reaching a threshold of said neural compartment, and delivers a generated spike signal to interconnected neural compartments of a next hierarchical level. Each neural compartment is further interconnected to one or more external spiking systems, such that said neural compartment integrates spike signals from interconnected external spiking systems, and delivers a generated spike signal to interconnected external spiking systems. The neural compartments of a neural module include one soma compartment and a plurality of dendrite compartments. Each neural compartment is excitatory or inhibitory.

摘要翻译： 本发明的实施例提供一种神经模块，其包括神经腔室的多级分级结构。 每个神经隔室与分层结构中的先前水平和下一层次级别的一个或多个神经隔室相互连接。 每个神经隔室整合来自先前分层级别的互连神经腔室的尖峰信号，响应于达到所述神经腔室的阈值的积分尖峰信号产生尖峰信号，并将产生的尖峰信号传递到下一层级的互连神经腔室 。 每个神经隔室进一步互连到一个或多个外部加标系统，使得所述神经腔室集成来自互连的外部加标系统的尖峰信号，并将产生的尖峰信号传送到互连的外部加标系统。 神经模块的神经腔室包括一个血管隔室和多个枝晶隔室。 每个神经室是兴奋性或抑制性的。

公开(公告)号：US20120084240A1

公开(公告)日：2012-04-05

申请号：US12895710

申请日：2010-09-30

申请人： Steven K. Esser ,  Dharmendra S. Modha ,  Anthony Ndirango ,  Bipin Rajendran

发明人： Steven K. Esser ,  Dharmendra S. Modha ,  Anthony Ndirango ,  Bipin Rajendran

IPC分类号： G06N3/04

CPC分类号： G06N3/063

摘要： Embodiments of the invention are directed to producing spike-timing dependent plasticity using electronic neurons for computation, and pattern matching tasks such as association and recall. In response to an electronic neuron spiking, a spiking signal is sent from the electronic neuron to each axon driver and each dendrite driver connected to the spiking electronic neuron. Each axon driver receiving the spiking signal sends an axonal signal from the axon driver to a variable state resistor. Each dendrite driver receiving the spiking signal sends a dendritic signal from the dendrite driver to the variable state resistor, wherein the variable state resistor couples the axon driver and the dendrite driver. The combination of the axonal and dendritic signals is capable of increasing or decreasing conductance of the variable state resistor.

摘要翻译： 本发明的实施例涉及使用用于计算的电子神经元和诸如关联和召回的模式匹配任务来产生尖峰时序相关的可塑性。 响应于电子神经元峰值，从电子神经元发送尖峰信号到每个轴突驱动器，并且每个枝晶驱动器连接到尖峰电子神经元。 接收尖峰信号的每个轴突驱动器将轴突信号从轴突驱动器发送到可变状态电阻器。 接收尖峰信号的每个枝晶驱动器将枝晶信号从枝晶驱动器发送到可变状态电阻器，其中可变状态电阻器耦合轴突驱动器和枝晶驱动器。 轴突和树突状信号的组合能够增加或降低可变状态电阻的电导。

公开(公告)号：US09269044B2

公开(公告)日：2016-02-23

申请号：US13585010

申请日：2012-08-14

申请人： Filipp Akopyan ,  John V. Arthur ,  Rajit Manohar ,  Paul A. Merolla ,  Dharmendra S. Modha ,  Alyosha Molnar ,  William P. Risk, III

发明人： Filipp Akopyan ,  John V. Arthur ,  Rajit Manohar ,  Paul A. Merolla ,  Dharmendra S. Modha ,  Alyosha Molnar ,  William P. Risk, III

IPC分类号： G06N3/04 ,  G06N3/063

CPC分类号： G06N3/06 ,  G06N3/04 ,  G06N3/049 ,  G06N3/063

摘要： An event-driven neural network includes a plurality of interconnected core circuits is provided. Each core circuit includes an electronic synapse array has multiple digital synapses interconnecting a plurality of digital electronic neurons. A synapse interconnects an axon of a pre-synaptic neuron with a dendrite of a post-synaptic neuron. A neuron integrates input spikes and generates a spike event in response to the integrated input spikes exceeding a threshold. Each core circuit also has a scheduler that receives a spike event and delivers the spike event to a selected axon in the synapse array based on a schedule for deterministic event delivery.

摘要翻译： 事件驱动神经网络包括多个互连的核心电路。 每个核心电路包括具有互连多个数字电子神经元的多个数字突触的电子突触阵列。 突触将突触前神经元的轴突与突触后神经元的枝晶相互连接。 神经元集成输入尖峰，并响应于超过阈值的积分输入尖峰而产生尖峰事件。 每个核心电路还具有接收尖峰事件的调度器，并且基于用于确定性事件递送的调度将突发事件传递到突触阵列中的选定轴突。

公开(公告)号：US09245222B2

公开(公告)日：2016-01-26

申请号：US13594069

申请日：2012-08-24

申请人： Dharmendra S. Modha

发明人： Dharmendra S. Modha

IPC分类号： G06E1/00 ,  G06N3/063 ,  G06N3/04 ,  G06F13/40

CPC分类号： G06N3/04 ,  G06F13/4068 ,  G06N3/063 ,  Y02D10/14 ,  Y02D10/151

摘要： Embodiments of the invention provide a neural network comprising multiple functional neural core circuits, and a dynamically reconfigurable switch interconnect between the functional neural core circuits. The interconnect comprises multiple connectivity neural core circuits. Each functional neural core circuit comprises a first and a second core module. Each core module comprises a plurality of electronic neurons, a plurality of incoming electronic axons, and multiple electronic synapses interconnecting the incoming axons to the neurons. Each neuron has a corresponding outgoing electronic axon. In one embodiment, zero or more sets of connectivity neural core circuits interconnect outgoing axons in a functional neural core circuit to incoming axons in the same functional neural core circuit. In another embodiment, zero or more sets of connectivity neural core circuits interconnect outgoing and incoming axons in a functional neural core circuit to incoming and outgoing axons in a different functional neural core circuit, respectively.

公开(公告)号：US09218564B2

公开(公告)日：2015-12-22

申请号：US13562195

申请日：2012-07-30

申请人： John V. Arthur ,  John E. Barth, Jr. ,  Paul A. Merolla ,  Dharmendra S. Modha

发明人： John V. Arthur ,  John E. Barth, Jr. ,  Paul A. Merolla ,  Dharmendra S. Modha

IPC分类号： G06N3/02 ,  G06N3/04 ,  G06N3/08

CPC分类号： G06N3/0635 ,  G06N3/04 ,  G06N3/049 ,  G06N3/063 ,  G06N3/08

摘要： Embodiments of the invention relate to providing transposable access to a synapse array using a recursive array layout. One embodiment comprises maintaining synaptic weights for multiple synapses connecting multiple axons and multiple neurons, wherein the synaptic weights are maintained based on a recursive array layout. The recursive array layout facilitates transposable access to the synaptic weights. A neuronal spike event between an axon and a neuron is communicated via a corresponding connecting synapse by accessing the synaptic weight of the corresponding connecting synapse in the recursive array layout.

摘要翻译： 本发明的实施例涉及使用递归阵列布局提供对突触阵列的可转位访问。 一个实施例包括维持连接多个轴突和多个神经元的多个突触的突触权重，其中基于递归阵列布局维持突触权重。 递归数组布局有助于对突触权重的可转位访问。 通过访问递归阵列布局中相应连接突触的突触权重，通过相应的连接突触传达轴突和神经元之间的神经元尖峰事件。

公开(公告)号：US20150302295A1

公开(公告)日：2015-10-22

申请号：US13563333

申请日：2012-07-31

申请人： Rodrigo Alvarez-Icaza Rivera ,  John V. Arthur ,  Andrew S. Cassidy ,  Paul A. Merolla ,  Dharmendra S. Modha

发明人： Rodrigo Alvarez-Icaza Rivera ,  John V. Arthur ,  Andrew S. Cassidy ,  Paul A. Merolla ,  Dharmendra S. Modha

IPC分类号： G06N3/08 ,  G06N3/04

CPC分类号： G06N3/04 ,  G06N3/049 ,  G06N3/063

摘要： Embodiments of the invention relate to a globally asynchronous and locally synchronous neuromorphic network. One embodiment comprises generating a synchronization signal that is distributed to a plurality of neural core circuits. In response to the synchronization signal, in at least one core circuit, incoming spike events maintained by said at least one core circuit are processed to generate an outgoing spike event. Spike events are asynchronously communicated between the core circuits via a routing fabric comprising multiple asynchronous routers.

摘要翻译： 本发明的实施例涉及全球异步和局部同步神经网络。 一个实施例包括生成分配给多个神经核心电路的同步信号。 响应于同步信号，在至少一个核心电路中，处理由所述至少一个核心电路维持的传入尖峰事件以产生输出尖峰事件。 尖峰事件通过包括多个异步路由器的路由结构在核心电路之间异步传送。

公开(公告)号：US09159020B2

公开(公告)日：2015-10-13

申请号：US13619433

申请日：2012-09-14

申请人： Rodrigo Alcarez-Icaza Rivera ,  John V. Arthur ,  Andrew S. Cassidy ,  Paul A. Merolla ,  Dharmendra S. Modha

发明人： Rodrigo Alcarez-Icaza Rivera ,  John V. Arthur ,  Andrew S. Cassidy ,  Paul A. Merolla ,  Dharmendra S. Modha

IPC分类号： G06N3/063 ,  G06N3/02 ,  G06N3/04

CPC分类号： G06N3/049 ,  G06N3/02 ,  G06N3/063

摘要： Embodiments of the invention relate to a multiplexed neural core circuit. One embodiment comprises a neural core circuit including a memory device that maintains neuronal attributes for multiple neurons. The memory device has multiple entries. Each entry maintains neuronal attributes for a corresponding neuron. The core circuit further comprises a controller for managing the memory device and processing neuronal firing events targeting each neuron. The controller multiplexes computation and control logic for the neurons. In response to neuronal firing events targeting one of the neurons, the controller retrieves neuronal attributes for the target neuron from a corresponding entry of the memory device, and integrates the firing events based on the retrieved neuronal attributes to generate a firing event for the target neuron.

摘要翻译： 本发明的实施例涉及多路神经核心电路。 一个实施例包括神经核心电路，其包括维持多个神经元的神经元属性的存储器件。 存储设备有多个条目。 每个条目保持相应神经元的神经元属性。 核心电路还包括用于管理存储器件并处理针对每个神经元的神经元触发事件的控制器。 控制器复用神经元的计算和控制逻辑。 响应于针对其中一个神经元的神经元发射事件，控制器从存储器件的相应入口检索目标神经元的神经元属性，并且基于所检索的神经元属性来集成触发事件以产生目标神经元的触发事件 。