-
公开(公告)号：US09275330B2
公开(公告)日：2016-03-01
申请号：US13596278
申请日：2012-08-28
CPC分类号： G06N3/04 , G06F9/44505 , G06N3/049 , G06N3/063 , G06N3/088
摘要： Embodiments of the invention provide a neural core circuit comprising a synaptic interconnect network including plural electronic synapses for interconnecting one or more source electronic neurons with one or more target electronic neurons. The interconnect network further includes multiple axon paths and multiple dendrite paths. Each synapse is at a cross-point junction of the interconnect network between a dendrite path and an axon path. The core circuit further comprises a routing module maintaining routing information. The routing module routes output from a source electronic neuron to one or more selected axon paths. Each synapse provides a configurable level of signal conduction from an axon path of a source electronic neuron to a dendrite path of a target electronic neuron.
-
2.发明授权Neuromorphic event-driven neural computing architecture in a scalable neural network 有权神经元事件驱动的神经计算架构在可扩展的神经网络中公开(公告)号：US09269044B2
公开(公告)日：2016-02-23
申请号：US13585010
申请日：2012-08-14
申请人： Filipp Akopyan , John V. Arthur , Rajit Manohar , Paul A. Merolla , Dharmendra S. Modha , Alyosha Molnar , William P. Risk, III
发明人： Filipp Akopyan , John V. Arthur , Rajit Manohar , Paul A. Merolla , Dharmendra S. Modha , Alyosha Molnar , William P. Risk, III
摘要： An event-driven neural network includes a plurality of interconnected core circuits is provided. Each core circuit includes an electronic synapse array has multiple digital synapses interconnecting a plurality of digital electronic neurons. A synapse interconnects an axon of a pre-synaptic neuron with a dendrite of a post-synaptic neuron. A neuron integrates input spikes and generates a spike event in response to the integrated input spikes exceeding a threshold. Each core circuit also has a scheduler that receives a spike event and delivers the spike event to a selected axon in the synapse array based on a schedule for deterministic event delivery.
摘要翻译： 事件驱动神经网络包括多个互连的核心电路。 每个核心电路包括具有互连多个数字电子神经元的多个数字突触的电子突触阵列。 突触将突触前神经元的轴突与突触后神经元的枝晶相互连接。 神经元集成输入尖峰，并响应于超过阈值的积分输入尖峰而产生尖峰事件。 每个核心电路还具有接收尖峰事件的调度器，并且基于用于确定性事件递送的调度将突发事件传递到突触阵列中的选定轴突。
-
公开(公告)号：US09245222B2
公开(公告)日：2016-01-26
申请号：US13594069
申请日：2012-08-24
申请人： Dharmendra S. Modha
发明人： Dharmendra S. Modha
CPC分类号： G06N3/04 , G06F13/4068 , G06N3/063 , Y02D10/14 , Y02D10/151
摘要： Embodiments of the invention provide a neural network comprising multiple functional neural core circuits, and a dynamically reconfigurable switch interconnect between the functional neural core circuits. The interconnect comprises multiple connectivity neural core circuits. Each functional neural core circuit comprises a first and a second core module. Each core module comprises a plurality of electronic neurons, a plurality of incoming electronic axons, and multiple electronic synapses interconnecting the incoming axons to the neurons. Each neuron has a corresponding outgoing electronic axon. In one embodiment, zero or more sets of connectivity neural core circuits interconnect outgoing axons in a functional neural core circuit to incoming axons in the same functional neural core circuit. In another embodiment, zero or more sets of connectivity neural core circuits interconnect outgoing and incoming axons in a functional neural core circuit to incoming and outgoing axons in a different functional neural core circuit, respectively.
-
4.发明授权Providing transposable access to a synapse array using a recursive array layout 有权使用递归数组布局提供对突触阵列的转座访问公开(公告)号：US09218564B2
公开(公告)日：2015-12-22
申请号：US13562195
申请日：2012-07-30
CPC分类号： G06N3/0635 , G06N3/04 , G06N3/049 , G06N3/063 , G06N3/08
摘要： Embodiments of the invention relate to providing transposable access to a synapse array using a recursive array layout. One embodiment comprises maintaining synaptic weights for multiple synapses connecting multiple axons and multiple neurons, wherein the synaptic weights are maintained based on a recursive array layout. The recursive array layout facilitates transposable access to the synaptic weights. A neuronal spike event between an axon and a neuron is communicated via a corresponding connecting synapse by accessing the synaptic weight of the corresponding connecting synapse in the recursive array layout.
摘要翻译： 本发明的实施例涉及使用递归阵列布局提供对突触阵列的可转位访问。 一个实施例包括维持连接多个轴突和多个神经元的多个突触的突触权重，其中基于递归阵列布局维持突触权重。 递归数组布局有助于对突触权重的可转位访问。 通过访问递归阵列布局中相应连接突触的突触权重，通过相应的连接突触传达轴突和神经元之间的神经元尖峰事件。
-
5.发明申请公开(公告)号：US20150302295A1
公开(公告)日：2015-10-22
申请号：US13563333
申请日：2012-07-31
申请人： Rodrigo Alvarez-Icaza Rivera , John V. Arthur , Andrew S. Cassidy , Paul A. Merolla , Dharmendra S. Modha
发明人： Rodrigo Alvarez-Icaza Rivera , John V. Arthur , Andrew S. Cassidy , Paul A. Merolla , Dharmendra S. Modha
摘要： Embodiments of the invention relate to a globally asynchronous and locally synchronous neuromorphic network. One embodiment comprises generating a synchronization signal that is distributed to a plurality of neural core circuits. In response to the synchronization signal, in at least one core circuit, incoming spike events maintained by said at least one core circuit are processed to generate an outgoing spike event. Spike events are asynchronously communicated between the core circuits via a routing fabric comprising multiple asynchronous routers.
摘要翻译： 本发明的实施例涉及全球异步和局部同步神经网络。 一个实施例包括生成分配给多个神经核心电路的同步信号。 响应于同步信号，在至少一个核心电路中，处理由所述至少一个核心电路维持的传入尖峰事件以产生输出尖峰事件。 尖峰事件通过包括多个异步路由器的路由结构在核心电路之间异步传送。
-
公开(公告)号：US09159020B2
公开(公告)日：2015-10-13
申请号：US13619433
申请日：2012-09-14
申请人： Rodrigo Alcarez-Icaza Rivera , John V. Arthur , Andrew S. Cassidy , Paul A. Merolla , Dharmendra S. Modha
发明人： Rodrigo Alcarez-Icaza Rivera , John V. Arthur , Andrew S. Cassidy , Paul A. Merolla , Dharmendra S. Modha
摘要： Embodiments of the invention relate to a multiplexed neural core circuit. One embodiment comprises a neural core circuit including a memory device that maintains neuronal attributes for multiple neurons. The memory device has multiple entries. Each entry maintains neuronal attributes for a corresponding neuron. The core circuit further comprises a controller for managing the memory device and processing neuronal firing events targeting each neuron. The controller multiplexes computation and control logic for the neurons. In response to neuronal firing events targeting one of the neurons, the controller retrieves neuronal attributes for the target neuron from a corresponding entry of the memory device, and integrates the firing events based on the retrieved neuronal attributes to generate a firing event for the target neuron.
摘要翻译： 本发明的实施例涉及多路神经核心电路。 一个实施例包括神经核心电路，其包括维持多个神经元的神经元属性的存储器件。 存储设备有多个条目。 每个条目保持相应神经元的神经元属性。 核心电路还包括用于管理存储器件并处理针对每个神经元的神经元触发事件的控制器。 控制器复用神经元的计算和控制逻辑。 响应于针对其中一个神经元的神经元发射事件，控制器从存储器件的相应入口检索目标神经元的神经元属性，并且基于所检索的神经元属性来集成触发事件以产生目标神经元的触发事件 。
-
公开(公告)号：US20150286924A1
公开(公告)日：2015-10-08
申请号：US13562187
申请日：2012-07-30
摘要： Embodiments of the invention relate to a scalable neural hardware for the noisy-OR model of Bayesian networks. One embodiment comprises a neural core circuit including a pseudo-random number generator for generating random numbers. The neural core circuit further comprises a plurality of incoming electronic axons, a plurality of neural modules, and a plurality of electronic synapses interconnecting the axons to the neural modules. Each synapse interconnects an axon with a neural module. Each neural module receives incoming spikes from interconnected axons. Each neural module represents a noisy-OR gate. Each neural module spikes probabilistically based on at least one random number generated by the pseudo-random number generator unit.
摘要翻译： 本发明的实施例涉及用于贝叶斯网络的噪声-OR模型的可伸缩神经硬件。 一个实施例包括神经核心电路，其包括用于产生随机数的伪随机数发生器。 神经核心电路还包括多个进入的电子轴突，多个神经模块和将轴突与神经模块相互连接的多个电子突触。 每个突触将轴突与神经模块相互连接。 每个神经模块从相互联系的轴突接收进入的尖峰。 每个神经模块表示噪声或门。 每个神经模块基于由伪随机数发生器单元生成的至少一个随机数来概率地尖峰。
-
8.发明授权Synaptic, dendritic, somatic, and axonal plasticity in a network of neural cores using a plastic multi-stage crossbar switching 有权使用塑料多级交叉开关的神经核心网络中的突触，树突状，体细胞和轴突可塑性公开(公告)号：US08977583B2
公开(公告)日：2015-03-10
申请号：US13434729
申请日：2012-03-29
申请人： Dharmendra S. Modha
发明人： Dharmendra S. Modha
CPC分类号： G06N3/04 , G06F13/4068 , G06N3/063 , Y02D10/14 , Y02D10/151
摘要： Embodiments of the invention provide a neural network comprising multiple functional neural core circuits, and a dynamically reconfigurable switch interconnect between the functional neural core circuits. The interconnect comprises multiple connectivity neural core circuits. Each functional neural core circuit comprises a first and a second core module. Each core module comprises a plurality of electronic neurons, a plurality of incoming electronic axons, and multiple electronic synapses interconnecting the incoming axons to the neurons. Each neuron has a corresponding outgoing electronic axon. In one embodiment, zero or more sets of connectivity neural core circuits interconnect outgoing axons in a functional neural core circuit to incoming axons in the same functional neural core circuit. In another embodiment, zero or more sets of connectivity neural core circuits interconnect outgoing and incoming axons in a functional neural core circuit to incoming and outgoing axons in a different functional neural core circuit, respectively.
摘要翻译： 本发明的实施例提供了一种包括多个功能神经核心电路的神经网络，以及功能神经核心电路之间的动态可重构开关互连。 互连包括多个连接神经核心电路。 每个功能神经核心电路包括第一和第二核心模块。 每个核心模块包括多个电子神经元，多个输入电子轴突以及将输入的轴突与神经元相互连接的多个电子突触。 每个神经元都有一个相应的输出电子轴突。 在一个实施例中，零个或多个连接神经核心电路组将功能性神经核心电路中的输出轴突与相同功能神经核心电路中的输入轴突相互连接。 在另一个实施例中，零个或多个连接神经核心电路组将功能性神经核心电路中的输出和输入轴突分别互连到不同功能神经核心电路中的输入和输出轴突。
-
9.发明授权Multi-processor cortical simulations with reciprocal connections with shared weights 有权多处理器皮质模拟与共享权重的互惠连接公开(公告)号：US08924322B2
公开(公告)日：2014-12-30
申请号：US13524798
申请日：2012-06-15
摘要： Embodiments of the invention relate to distributed simulation frameworks that provide reciprocal communication. One embodiment comprises interconnecting neuron groups on different processors via a plurality of reciprocal communication pathways, and facilitating the exchange of reciprocal spiking communication between two different processors using at least one Ineuron module. Each processor includes at least one neuron group. Each neuron group includes at least one electronic neuron.
摘要翻译： 本发明的实施例涉及提供相互通信的分布式仿真框架。 一个实施例包括经由多个相互通信路径在不同处理器上互连神经元组，并且促进使用至少一个Ineuron模块交换两个不同处理器之间的相互加速通信。 每个处理器包括至少一个神经元组。 每个神经元组包括至少一个电子神经元。
-
公开(公告)号：US08892487B2
公开(公告)日：2014-11-18
申请号：US12982505
申请日：2010-12-30
IPC分类号： G06F15/18
CPC分类号： G06N3/08 , G06N3/063 , G06N3/0635 , G11C11/54
摘要： Embodiments of the invention provide electronic synapse devices for reinforcement learning. An electronic synapse is configured for interconnecting a pre-synaptic electronic neuron and a post-synaptic electronic neuron. The electronic synapse comprises memory elements configured for storing a state of the electronic synapse and storing meta information for updating the state of the electronic synapse. The electronic synapse further comprises an update module configured for updating the state of the electronic synapse based on the meta information in response to an update signal for reinforcement learning. The update module is configured for updating the state of the electronic synapse based on the meta information, in response to a delayed update signal for reinforcement learning based on a learning rule.
摘要翻译： 本发明的实施例提供用于加强学习的电子突触装置。 配置电子突触以互连预突触电子神经元和突触后电子神经元。 电子突触包括配置用于存储电子突触的状态并存储用于更新电子突触的状态的元信息的存储器元件。 电子突变还包括更新模块，该更新模块被配置为响应于用于加强学习的更新信号，基于元信息来更新电子突触的状态。 更新模块被配置为响应于用于基于学习规则的加强学习的延迟更新信号，基于元信息来更新电子突触的状态。
-
-
-
-
-
-
-
-
-
搜索结果
100 条记录 (耗时 0.018 秒)
