公开(公告)号：US20080195325A1

公开(公告)日：2008-08-14

申请号：US12103804

申请日：2008-04-16

申请人： Rajiv V. Joshi ,  Rouwaida N. Kanj ,  Sani R. Nassif

发明人： Rajiv V. Joshi ,  Rouwaida N. Kanj ,  Sani R. Nassif

IPC分类号： G01N33/00

CPC分类号： G06F17/5036 ,  G11C29/028 ,  G11C29/54 ,  G11C29/56004 ,  G11C29/56008 ,  G11C2029/0403

摘要： A system and computer program for efficient cell failure rate estimation in cell arrays provides an efficient mechanism for raising the performance of memory arrays beyond present levels/yields. An initial search is performed across cell circuit parameters to determine failures with respect to a set of performance variables. For a single failure region the initial search can be a uniform sampling of the parameter space and when enough failure points have been accumulated, a mean is chosen from the mean of the detected failure points. Mixture importance sampling (MIS) is then performed to efficiently estimate the single failure region. For multiple failure regions, a particular failure region is selected by varying the memory circuit cell parameters along a random set of vectors until failures are detected, thus identifying the boundary of the failure region of interest as the closest failure region. A new mean is chosen for MIS in conformity with the location of the detected boundary.

摘要翻译： 用于在单元阵列中有效的单元故障率估计的系统和计算机程序为提高存储器阵列的性能提供了超出当前水平/产量的有效机制。 在单元电路参数之间执行初始搜索以确定关于一组性能变量的故障。 对于单个故障区域，初始搜索可以是参数空间的均匀采样，并且当已经累积了足够的故障点时，从检测到的故障点的平均值中选择一个平均值。 然后执行混合重要性采样（MIS）以有效地估计单个故障区域。 对于多个故障区域，通过沿随机矢量集改变存储器电路单元参数直到检测到故障来选择特定故障区域，从而将感兴趣的故障区域的边界识别为最接近的故障区域。 根据检测到的边界的位置，为MIS选择新的平均值。

公开(公告)号：US07380225B2

公开(公告)日：2008-05-27

申请号：US11375477

申请日：2006-03-14

申请人： Rajiv V. Joshi ,  Rouwaida N. Kanj ,  Sani R. Nassif

发明人： Rajiv V. Joshi ,  Rouwaida N. Kanj ,  Sani R. Nassif

IPC分类号： G06F17/50

CPC分类号： G06F17/5036 ,  G11C29/028 ,  G11C29/54 ,  G11C29/56004 ,  G11C29/56008 ,  G11C2029/0403

摘要： A method and computer program for efficient cell failure rate estimation in cell arrays provides an efficient mechanism for raising the performance of memory arrays beyond present levels/yields. An initial search is performed across cell circuit parameters to determine failures with respect to a set of performance variables. For a single failure region the initial search can be a uniform sampling of the parameter space and when enough failure points have been accumulated, a mean is chosen from the mean of the detected failure points. Mixture importance sampling (MIS) is then performed to efficiently estimate the single failure region. For multiple failure regions, a particular failure region is selected by varying the memory circuit cell parameters along a random set of vectors until failures are detected, thus identifying the boundary of the failure region of interest as the closest failure region. A new mean is chosen for MIS in conformity with the location of the detected boundary.

摘要翻译： 用于在单元阵列中有效的单元故障率估计的方法和计算机程序提供了一种有效的机制，用于提高存储器阵列的性能超过现有水平/产量。 在单元电路参数之间执行初始搜索以确定关于一组性能变量的故障。 对于单个故障区域，初始搜索可以是参数空间的均匀采样，并且当已经累积了足够的故障点时，从检测到的故障点的平均值中选择一个平均值。 然后执行混合重要性采样（MIS）以有效地估计单个故障区域。 对于多个故障区域，通过沿随机矢量集改变存储器电路单元参数直到检测到故障来选择特定故障区域，从而将感兴趣的故障区域的边界识别为最接近的故障区域。 根据检测到的边界的位置，为MIS选择新的平均值。

公开(公告)号：US08346528B2

公开(公告)日：2013-01-01

申请号：US12551777

申请日：2009-09-01

申请人： Rajiv V. Joshi ,  Rouwaida N. Kanj ,  Sani R. Nassif

发明人： Rajiv V. Joshi ,  Rouwaida N. Kanj ,  Sani R. Nassif

IPC分类号： G06F17/50

CPC分类号： G06F17/5036

摘要： Mechanisms are provided for modeling a plurality of devices of an integrated circuit design as a single statistically equivalent wide device. An integrated circuit design is analyzed to identify a portion of the integrated circuit design having the plurality of devices. For the plurality of devices, a statistical model of a single statistically equivalent wide device is generated which has a statistical distribution of at least one operating characteristic of the single statistically equivalent wide device that captures statistical operating characteristic distributions of individual devices in the plurality of devices. At least one statistical operating characteristic of the single statistically equivalent wide device is a complex non-linear function of the statistical operating characteristics of the individual devices. The integrated circuit design is modeled using the single statistically equivalent wide device.

摘要翻译： 提供了用于将集成电路设计的多个装置建模为单个统计上等同的宽装置的机构。 分析集成电路设计以识别具有多个装置的集成电路设计的一部分。 对于多个装置，产生统计模型的单个统计学上等效的宽装置，该统计模型具有捕获多个装置中的各个装置的统计工作特性分布的单个统计学等效的宽装置的至少一个操作特性的统计分布 。 单个统计学等效的宽设备的至少一个统计工作特性是各个设备的统计操作特性的复杂非线性函数。 集成电路设计采用单一统计学上等效的宽设备进行建模。

公开(公告)号：US20120046929A1

公开(公告)日：2012-02-23

申请号：US12859871

申请日：2010-08-20

申请人： Rajiv V. Joshi ,  Rouwaida N. Kanj ,  Sani R. Nassif ,  Carl J. Radens

发明人： Rajiv V. Joshi ,  Rouwaida N. Kanj ,  Sani R. Nassif ,  Carl J. Radens

IPC分类号： G06F17/50

CPC分类号： G06F11/076 ,  G06F11/008 ,  G06F11/079 ,  G06F17/5009 ,  G06F17/5022 ,  G06F2217/10

摘要： A mechanism is provided for reusing importance sampling for efficient cell failure rate estimation of process variations and other design considerations. First, the mechanism performs a search across circuit parameters to determine failures with respect to a set of performance variables. For a single failure region, the initial search may be a uniform sampling of the parameter space. Mixture importance sampling (MIS) efficiently may estimate the single failure region. The mechanism then finds a center of gravity for each metric and finds importance samples. Then, for each new origin corresponding to a process variation or other design consideration, the mechanism finds a suitable projection and recomputes new importance sampling (IS) ratios.

摘要翻译： 提供了一种用于重用采样的机制，用于有效地进行细胞故障率估计过程变化和其他设计考虑。 首先，该机制对电路参数进行搜索，以确定相对于一组性能变量的故障。 对于单个故障区域，初始搜索可以是参数空间的均匀采样。 混合重要性抽样（MIS）有效地估计单个故障区域。 然后，该机制找到每个度量的重心，并发现重要性样本。 然后，对于对应于过程变化或其他设计考虑的每个新的原点，机制找到合适的投影并重新计算新的重要性抽样（IS）比率。

公开(公告)号：US07995418B2

公开(公告)日：2011-08-09

申请号：US12399551

申请日：2009-03-06

申请人： Rajiv V. Joshi ,  Jente B Kuang ,  Rouwaida N. Kanj ,  Sani R. Nassif ,  Hung Cai Ngo

发明人： Rajiv V. Joshi ,  Jente B Kuang ,  Rouwaida N. Kanj ,  Sani R. Nassif ,  Hung Cai Ngo

IPC分类号： G11C5/14

CPC分类号： G11C11/417 ,  G11C5/14

摘要： A method and computer program product for controlling a storage device using per-element selectable power supply voltages provides energy conservation in storage devices while maintaining a particular performance level. The storage device is partitioned into multiple elements, which may be sub-arrays, rows, columns or individual storage cells. Each element has a corresponding virtual power supply rail that is provided with a selectable power supply voltage. The power supply voltage provided to the virtual power supply rail for an element is set to the minimum power supply voltage unless a higher power supply voltage is required for the element to meet performance requirements. A control cell may be provided within each element that provides a control signal that selects the power supply voltage supplied to the corresponding virtual power supply rail. The state of the cell may be set via a fuse or mask, or values may be loaded into the control cells at initialization of the storage device.

摘要翻译： 用于使用每元素可选择的电源电压来控制存储设备的方法和计算机程序产品在保持特定性能水平的同时在存储设备中提供节能。 存储设备被划分成多个元素，其可以是子阵列，行，列或单独的存储单元。 每个元件具有相应的虚拟电源轨，其具有可选择的电源电压。 提供给用于元件的虚拟电源轨的电源电压被设置为最小电源电压，除非元件满足性能要求需要更高的电源电压。 可以在每个元件内提供控制单元，其提供选择提供给相应的虚拟电源轨的电源电压的控制信号。 可以通过熔丝或掩模设置单元的状态，或者可以在存储设备初始化时将值加载到控制单元中。

公开(公告)号：US20110054856A1

公开(公告)日：2011-03-03

申请号：US12551777

申请日：2009-09-01

申请人： Rajiv V. Joshi ,  Rouwaida N. Kanj ,  Sani R. Nassif

发明人： Rajiv V. Joshi ,  Rouwaida N. Kanj ,  Sani R. Nassif

IPC分类号： G06F7/60 ,  G06G7/62

CPC分类号： G06F17/5036

摘要： Mechanisms are provided for modeling a plurality of devices of an integrated circuit design as a single statistically equivalent wide device. An integrated circuit design is analyzed to identify a portion of the integrated circuit design having the plurality of devices. For the plurality of devices, a statistical model of a single statistically equivalent wide device is generated which has a statistical distribution of at least one operating characteristic of the single statistically equivalent wide device that captures statistical operating characteristic distributions of individual devices in the plurality of devices. At least one statistical operating characteristic of the single statistically equivalent wide device is a complex non-linear function of the statistical operating characteristics of the individual devices. The integrated circuit design is modeled using the single statistically equivalent wide device.

摘要翻译： 提供了用于将集成电路设计的多个装置建模为单个统计上等同的宽装置的机构。 分析集成电路设计以识别具有多个装置的集成电路设计的一部分。 对于多个装置，产生统计模型的单个统计学上等效的宽装置，该统计模型具有捕获多个装置中的各个装置的统计工作特性分布的单个统计学等效的宽装置的至少一个操作特性的统计分布 。 单个统计学等效的宽设备的至少一个统计工作特性是各个设备的统计操作特性的复杂非线性函数。 集成电路设计采用单一统计学上等效的宽设备进行建模。

公开(公告)号：US07827018B2

公开(公告)日：2010-11-02

申请号：US11941183

申请日：2007-11-16

申请人： Chad A. Adams ,  Rajiv V. Joshi ,  Rouwaida N. Kanj ,  Sani R. Nassif

发明人： Chad A. Adams ,  Rajiv V. Joshi ,  Rouwaida N. Kanj ,  Sani R. Nassif

IPC分类号： G06F17/50

CPC分类号： G11C29/56008 ,  G11C29/82

摘要： A method and computer program for selecting circuit repairs using redundant elements with consideration of aging effects provides a mechanism for raising short-term and long-term performance of memory arrays beyond present levels/yields. Available redundant elements are used as replacements for selected elements in the array. The elements for replacement are selected by BOL (beginning-of-life) testing at a selected operating point that maximizes the end-of-life (EOL) yield distribution as among a set of operating points at which post-repair yield requirements are met at beginning-of-life (BOL). The selected operating point is therefore the “best” operating point to improve yield at EOL for a desired range of operating points or maximize the EOL operating range. For a given BOL repair operating point, the yield at EOL is computed. The operating point having the best yield at EOL is selected and testing is performed at that operating point to select repairs.

摘要翻译： 考虑到老化效应，使用冗余元件选择电路修复的方法和计算机程序提供了一种用于提高存储器阵列的短期和长期性能的机制，超过现有水平/产量。 可用的冗余元素用作数组中所选元素的替换。 通过在选定的操作点进行BOL（开始使用寿命）测试来选择最终使用寿命终止（EOL）产量分配的元素作为满足修复后产量要求的一组工作点 在生命初期（BOL）。 因此，所选择的操作点是“最佳”操作点，以提高EOL对于所需工作点范围的收益或最大化EOL操作范围。 对于给定的BOL修复操作点，计算EOL的收益率。 选择在EOL具有最佳产量的操作点，并在该操作点进行测试以选择修理。

公开(公告)号：US07551508B2

公开(公告)日：2009-06-23

申请号：US11941168

申请日：2007-11-16

申请人： Rajiv V. Joshi ,  Jente B Kuang ,  Rouwaida N. Kanj ,  Sani R. Nassif ,  Hung Cai Ngo

发明人： Rajiv V. Joshi ,  Jente B Kuang ,  Rouwaida N. Kanj ,  Sani R. Nassif ,  Hung Cai Ngo

IPC分类号： G11C5/14

CPC分类号： G11C11/417 ,  G11C5/14

摘要： An energy efficient storage device using per-element selectable power supply voltages provides energy conservation in storage devices while maintaining a particular performance level. The storage device is partitioned into multiple elements, which may be sub-arrays, rows, columns or individual storage cells. Each element has a corresponding virtual power supply rail that is provided with a selectable power supply voltage. The power supply voltage provided to the virtual power supply rail for an element is set to the minimum power supply voltage unless a higher power supply voltage is required for the element to meet performance requirements. A control cell may be provided within each element that provides a control signal that selects the power supply voltage supplied to the corresponding virtual power supply rail. The state of the cell may be set via a fuse or mask, or values may be loaded into the control cells at initialization of the storage device.

摘要翻译： 使用每元件可选择的电源电压的节能存储装置在保持特定的性能水平的同时在存储装置中提供节能。 存储设备被划分成多个元素，其可以是子阵列，行，列或单独的存储单元。 每个元件具有相应的虚拟电源轨，其具有可选择的电源电压。 提供给用于元件的虚拟电源轨的电源电压被设置为最小电源电压，除非元件满足性能要求需要更高的电源电压。 可以在每个元件内提供控制单元，其提供选择提供给相应的虚拟电源轨的电源电压的控制信号。 可以通过熔丝或掩模设置单元的状态，或者可以在存储设备初始化时将值加载到控制单元中。

公开(公告)号：US20130289965A1

公开(公告)日：2013-10-31

申请号：US13457722

申请日：2012-04-27

申请人： Rajiv V. Joshi ,  Rouwaida N. Kanj ,  Keunwoo Kim

发明人： Rajiv V. Joshi ,  Rouwaida N. Kanj ,  Keunwoo Kim

IPC分类号： G06F17/50

CPC分类号： G06F17/5068 ,  G06F2217/10

摘要： A method for analyzing circuits includes identifying one or more device zones in a full device structure. The device zones provide areas of interest to be analyzed. A partial device is generated that representatively includes the one or more device zones. Analytical meshes of the partial device are reduced by employing physical characteristics of the full device structure. The partial device is simulated, using a processor, to obtain device output information in the areas of interest that is representative of the full device structure. Systems are also disclosed.

公开(公告)号：US20130289948A1

公开(公告)日：2013-10-31

申请号：US13611359

申请日：2012-09-12

申请人： Rajiv V. Joshi ,  Rouwaida N. Kanj ,  Keunwoo Kim

发明人： Rajiv V. Joshi ,  Rouwaida N. Kanj ,  Keunwoo Kim

IPC分类号： G06F17/50

CPC分类号： G06F17/5068 ,  G06F2217/10

摘要： A method for analyzing circuits includes identifying one or more device zones in a full device structure. The device zones provide areas of interest to be analyzed. A partial device is generated that representatively includes the one or more device zones. Analytical meshes of the partial device are reduced by employing physical characteristics of the full device structure. The partial device is simulated, using a processor, to obtain device output information in the areas of interest that is representative of the full device structure. Systems are also disclosed.

摘要翻译： 一种用于分析电路的方法包括识别完整设备结构中的一个或多个设备区域。 设备区域提供要分析的感兴趣区域。 生成代表性地包括一个或多个设备区域的部分设备。 通过采用整个装置结构的物理特性来减少部分装置的分析网格。 使用处理器来模拟部分设备，以获得代表整个设备结构的感兴趣区域中的设备输出信息。 还披露了系统。