公开(公告)号：US20190146691A1

公开(公告)日：2019-05-16

申请号：US16243651

申请日：2019-01-09

Applicant: Futurewei Technologies, Inc.

Inventor： Yiren Huang

IPC: G06F3/06 ,  G06F11/10 ,  G11C29/00 ,  G11C29/52 ,  G06F12/02

CPC classification number: G06F3/0619 ,  G06F3/0629 ,  G06F3/0638 ,  G06F3/064 ,  G06F3/0688 ,  G06F3/0689 ,  G06F11/106 ,  G06F11/1068 ,  G06F11/108 ,  G06F12/0246 ,  G06F2212/7208 ,  G11C29/52 ,  G11C29/82 ,  Y02D10/13

Abstract: A solid state drive (SSD) employing a redundant array of independent disks (RAID) scheme includes a flash memory chip, erasable blocks in the flash memory chip, and a flash controller. The erasable blocks are configured to store flash memory pages. The flash controller is operably coupled to the flash memory chip. The flash controller is also configured to organize certain of the flash memory pages into a RAID line group and to write RAID line group membership information to each of the flash memory pages in the RAID line group.

公开(公告)号：US10083753B2

公开(公告)日：2018-09-25

申请号：US15842476

申请日：2017-12-14

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Francesco La Rosa ,  Gineuve Alieri

IPC: G11C14/00 ,  G11C29/00 ,  G11C16/26 ,  G11C16/10 ,  G11C16/16

CPC classification number: G11C14/0018 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  G11C29/76 ,  G11C29/785 ,  G11C29/789 ,  G11C29/82 ,  G11C29/84 ,  G11C29/846

Abstract: A non-volatile memory is erasable by page and equipped with a row redundancy mechanism. In the case of the detection of a defective row of the memory plane, the storing of the address of the row in a non-volatile register is carried out and a redundant row having a new address is assigned. In the case of an attempt to write to the defective row, a write to the redundant row is carried out. When writing to the redundant row, the new content of the redundant row is loaded into a volatile memory and, following an operation for writing to any other row of the memory plane, a re-loading of the new content of the redundant row into the volatile memory.

公开(公告)号：US20180181326A1

公开(公告)日：2018-06-28

申请号：US15701656

申请日：2017-09-12

Applicant: SK hynix Inc.

Inventor： Se-Hyun KIM

IPC: G06F3/06 ,  G11C16/10 ,  G11C29/00 ,  G06F11/10 ,  G11C16/26 ,  G06F11/07 ,  G11C16/34

CPC classification number: G06F3/0619 ,  G06F3/064 ,  G06F3/0679 ,  G06F11/073 ,  G06F11/1048 ,  G11C16/107 ,  G11C16/26 ,  G11C16/3404 ,  G11C29/82

Abstract: A memory system includes: a memory device including a plurality of memory blocks; and a controller suitable for selecting one or more first memory blocks based on a predetermined condition among the plurality of the memory blocks in a booting section, and increasing a read reclaim count value of one or more second memory blocks among the one or more first memory blocks for which a number of failed bits of read data exceeds a predetermined threshold.

公开(公告)号：US09996438B2

公开(公告)日：2018-06-12

申请号：US15638042

申请日：2017-06-29

Applicant: Intel Corporation

Inventor： Toru Tanzawa

IPC: G06F11/20

CPC classification number: G06F11/2094 ,  G06F3/0689 ,  G06F11/1076 ,  G06F11/2017 ,  G06F2201/805 ,  G06F2201/82 ,  G11C29/82

Abstract: An integrated circuit (IC) includes addressable blocks of memory, and at least one redundant block of memory. A block of memory includes two or more chunks of memory. The IC also includes redundancy control cells. Control circuitry is included to access a first chunk of a redundant block of memory in place of a first remapped chunk one of the addressable blocks of memory, and a second chunk of a redundant block of memory in place of a second remapped chunk one of the addressable blocks of memory, based on the redundancy control cells.

公开(公告)号：US20180151251A1

公开(公告)日：2018-05-31

申请号：US15695279

申请日：2017-09-05

Applicant: SK hynix Inc.

Inventor： Ik-Sung OH ,  Byeong-Gyu PARK ,  Kyu-Min LEE

IPC: G11C29/00 ,  G11C29/42 ,  G06F3/06

CPC classification number: G11C29/82 ,  G06F3/0619 ,  G06F3/064 ,  G11C29/42 ,  G11C29/4401 ,  G11C29/76

Abstract: A memory system may include: a memory device including a plurality of memory blocks configured in a plurality of super memory blocks; and a controller suitable for detecting two or more bad super memory blocks each including at least one bad block among the super memory blocks, selecting at least one victim super memory block among the bad super memory blocks, and replacing the at least one bad block in each remaining bad super memory block with at least one normal block of the victim super memory block.

公开(公告)号：US20180151244A1

公开(公告)日：2018-05-31

申请号：US15821871

申请日：2017-11-24

Applicant: Infineon Technologies AG

Inventor： Jan Otterstedt ,  Robin Boch ,  Gerd Dirscherl ,  Bernd Meyer ,  Christian Peters ,  Steffen Sonnekalb

IPC: G11C29/02 ,  G11C7/06

CPC classification number: G11C29/025 ,  G11C7/06 ,  G11C29/12005 ,  G11C29/702 ,  G11C29/82 ,  G11C2029/1202 ,  G11C2029/4402

Abstract: A memory circuit may include a plurality of electrically programmable memory cells arranged in a non-volatile memory cell array along a rows and columns, a plurality of word lines, each word line coupled with one or more memory cells, a plurality of non-volatile marking memory cells, wherein at least one word line of the plurality of word lines is associated with one or more marking memory cells, and a plurality of marking bit lines, each associated with marking memory cells, a plurality of marking source lines, each associated with marking memory cells, wherein, for marking memory cells, a physical connection from an associated marking source line and/or from an associated marking bit line to the marking memory cells defines those marking memory cells to a non-changeable state, wherein the marking memory cells are configured to identify the associated word line of respective marking memory cells in the non-changeable memory state.

公开(公告)号：US20180108413A1

公开(公告)日：2018-04-19

申请号：US15842476

申请日：2017-12-14

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Francesco La Rosa ,  Gineuve Alieri

IPC: G11C14/00 ,  G11C29/00 ,  G11C16/10 ,  G11C16/26 ,  G11C16/16

CPC classification number: G11C14/0018 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  G11C29/76 ,  G11C29/785 ,  G11C29/789 ,  G11C29/82 ,  G11C29/84 ,  G11C29/846

Abstract: A non-volatile memory is erasable by page and equipped with a row redundancy mechanism. In the case of the detection of a defective row of the memory plane, the storing of the address of the row in a non-volatile register is carried out and a redundant row having a new address is assigned. In the case of an attempt to write to the defective row, a write to the redundant row is carried out. When writing to the redundant row, the new content of the redundant row is loaded into a volatile memory and, following an operation for writing to any other row of the memory plane, a re-loading of the new content of the redundant row into the volatile memory.

公开(公告)号：US09911509B2

公开(公告)日：2018-03-06

申请号：US14099551

申请日：2013-12-06

Applicant: Intel Corporation

Inventor： Ravi H. Motwani

IPC: G11C29/00 ,  G11C29/44 ,  G11C29/42 ,  G11C29/04

CPC classification number: G11C29/44 ,  G11C29/42 ,  G11C29/82 ,  G11C2029/0409 ,  G11C2029/0411

Abstract: Methods and apparatus related to utilization of counter(s) for locating faulty die in a distributed codeword storage system are described. In one embodiment, first logic determines a plurality of values. Each of the plurality of values corresponds to a number of zeros or a number of ones in bits read from a portion of each of a plurality of memory dies. Second logic determines one or more candidates as a faulty die amongst the plurality of memory dies based at least in part on a comparison of the plurality of values for the plurality of memory dies. Other embodiments are also disclosed and claimed.

公开(公告)号：US20170300395A1

公开(公告)日：2017-10-19

申请号：US15638042

申请日：2017-06-29

Applicant: Intel Corporation

Inventor： Toru TANZAWA

IPC: G06F11/20

CPC classification number: G06F11/2094 ,  G06F3/0689 ,  G06F11/1076 ,  G06F11/2017 ,  G06F2201/805 ,  G06F2201/82 ,  G11C29/82

Abstract: An integrated circuit (IC) includes addressable blocks of memory, and at least one redundant block of memory. A block of memory includes two or more chunks of memory. The IC also includes redundancy control cells. Control circuitry is included to access a first chunk of a redundant block of memory in place of a first remapped chunk one of the addressable blocks of memory, and a second chunk of a redundant block of memory in place of a second remapped chunk one of the addressable blocks of memory, based on the redundancy control cells.

公开(公告)号：US09786388B1

公开(公告)日：2017-10-10

申请号：US14050249

申请日：2013-10-09

Applicant: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.

Inventor： Amir Nassie

IPC: G11C29/56 ,  G11C29/00 ,  G11C29/04 ,  G11C29/12 ,  G06F12/02 ,  G06F11/10 ,  G11C29/44

CPC classification number: G06F11/1068 ,  G06F12/0246 ,  G11C29/00 ,  G11C29/04 ,  G11C29/12 ,  G11C29/4401 ,  G11C29/52 ,  G11C29/72 ,  G11C29/804 ,  G11C29/82 ,  G11C2029/0409 ,  G11C2029/0411 ,  G11C2029/1208 ,  G11C2029/3602 ,  G11C2029/4002 ,  G11C2029/4402 ,  G11C2029/5606

Abstract: A system, computer readable medium and a method. The method may include sending input data to a NAND flash memory unit that comprises the NAND flash memory array and instructing the NAND flash memory unit to write input data to the NAND flash memory array to provide programmed data; reading from the NAND flash memory array the programmed data to provide read data; comparing the input data and the read data to provide column errors statistics at a column resolution; and defining, by a flash memory controller, bad columns of the NAND flash memory array in response to the column error statistics.