Memory module threading with staggered data transfers

    公开(公告)号:US10705988B2

    公开(公告)日:2020-07-07

    申请号:US16365528

    申请日:2019-03-26

    Applicant: Rambus Inc.

    Abstract: A method of transferring data between a memory controller and at least one memory module via a primary data bus having a primary data bus width is disclosed. The method includes accessing a first one of a memory device group via a corresponding data bus path in response to a threaded memory request from the memory controller. The accessing results in data groups collectively forming a first data thread transferred across a corresponding secondary data bus path. Transfer of the first data thread across the primary data bus width is carried out over a first time interval, while using less than the primary data transfer continuous throughput during that first time interval. During the first time interval, at least one data group from a second data thread is transferred on the primary data bus.

    Memory module threading with staggered data transfers
    22.
    发明授权
    Memory module threading with staggered data transfers 有权
    具有交错数据传输的内存模块线程

    公开(公告)号:US09569393B2

    公开(公告)日:2017-02-14

    申请号:US13963391

    申请日:2013-08-09

    Applicant: Rambus Inc.

    Abstract: A method of transferring data between a memory controller and at least one memory module via a primary data bus having a primary data bus width is disclosed. The method includes accessing a first one of a memory device group via a corresponding data bus path in response to a threaded memory request from the memory controller. The accessing results in data groups collectively forming a first data thread transferred across a corresponding secondary data bus path. Transfer of the first data thread across the primary data bus width is carried out over a first time interval, while using less than the primary data transfer continuous throughput during that first time interval. During the first time interval, at least one data group from a second data thread is transferred on the primary data bus.

    Abstract translation: 公开了一种通过具有主数据总线宽度的主数据总线在存储器控制器和至少一个存储器模块之间传送数据的方法。 该方法包括响应于来自存储器控制器的螺纹存储器请求经由对应的数据总线路径访问存储器件组中的第一个。 访问导致数据组共同形成通过对应的辅助数据总线路径传送的第一数据线程。 第一数据线程跨越主数据总线宽度的传输是在第一时间间隔内执行的,而在该第一时间间隔期间使用少于主数据传输连续吞吐量。 在第一时间间隔期间,在主数据总线上传送来自第二数据线程的至少一个数据组。

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