公开(公告)号：US11669754B2

公开(公告)日：2023-06-06

申请号：US16872194

申请日：2020-05-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Nima Elyasi ,  Vikas Sinha ,  Qinling Zheng ,  Changho Choi

IPC: G06F21/00 ,  G06N5/04 ,  G06F16/23 ,  G06N20/00 ,  G06Q10/0631

CPC classification number: G06N5/04 ,  G06F16/2379 ,  G06N20/00 ,  G06Q10/06315

Abstract: In a method for training a machine learning model, the method includes: segmenting, by a processor, a dataset from a database into one or more datasets based on time period windows; assigning, by the processor, one or more weighted values to the one or more datasets according to the time period windows of the one or more datasets; generating, by the processor, a training dataset from the one or more datasets according to the one or more weighted values; and training, by the processor, the machine learning model using the training dataset.

公开(公告)号：US11657300B2

公开(公告)日：2023-05-23

申请号：US15931573

申请日：2020-05-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Qinling Zheng ,  Nima Elyasi ,  Vikas Sinha ,  Changho Choi

IPC: G06N5/04 ,  G06N20/00 ,  G06F11/16

CPC classification number: G06N5/04 ,  G06F11/16 ,  G06N20/00

Abstract: A method for predicting a time-to-failure of a target storage device may include training a machine learning scheme with a time-series dataset, and applying the telemetry data from the target storage device to the machine learning scheme which may output a time-window based time-to-failure prediction. A method for training a machine learning scheme for predicting a time-to-failure of a storage device may include applying a data quality improvement framework to a time-series dataset of operational and failure data from multiple storage devices, and training the scheme with the pre-processed dataset. A method for training a machine learning scheme for predicting a time-to-failure of a storage device may include training the scheme with a first portion of a time-series dataset of operational and failure data from multiple storage devices, testing the machine learning scheme with a second portion of the time-series dataset, and evaluating the machine learning scheme.

公开(公告)号：US11055221B2

公开(公告)日：2021-07-06

申请号：US16424452

申请日：2019-05-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Vikas Sinha ,  Hien Le ,  Tarun Nakra ,  Yingying Tian ,  Apurva Patel ,  Omar Torres

IPC: G06F12/08 ,  G06F12/0831 ,  G06F11/07 ,  G06F12/0868

Abstract: According to one general aspect, an apparatus may include a processor configured to issue a first request for a piece of data from a cache memory and a second request for the piece of data from a system memory. The apparatus may include the cache memory configured to temporarily store a subset of data. The apparatus may include a memory interconnect. The a memory interconnect may be configured to receive the second request for the piece of data from the system memory. The a memory interconnect may be configured to determine if the piece of memory is stored in the cache memory. The a memory interconnect may be configured to, if the piece of memory is determined to be stored in the cache memory, cancel the second request for the piece of data from the system memory.

公开(公告)号：US10963388B2

公开(公告)日：2021-03-30

申请号：US16543503

申请日：2019-08-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Vikas Sinha ,  Teik Tan ,  Tarun Nakra

IPC: G06F12/08 ,  G06F12/0862 ,  G06F12/0811 ,  G06F13/40

Abstract: According to one general aspect, an apparatus may include a multi-tiered cache system that includes at least one upper cache tier relatively closer, hierarchically, to a processor and at least one lower cache tier relatively closer, hierarchically, to a system memory. The apparatus may include a memory interconnect circuit hierarchically between the multi-tiered cache system and the system memory. The apparatus may include a prefetcher circuit coupled with a lower cache tier of the multi-tiered cache system, and configured to issue a speculative prefetch request to the memory interconnect circuit for data to be placed into the lower cache tier. The memory interconnect circuit may be configured to cancel the speculative prefetch request if the data exists in an upper cache tier of the multi-tiered cache system.