Dynamic trigger compensation in OFDM systems

    公开(公告)号:US10999116B1

    公开(公告)日:2021-05-04

    申请号:US16655822

    申请日:2019-10-17

    Abstract: Systems and methods for enabling pre-compensation of timing offsets in OFDM receivers without invalidating channel estimates are described. Timing offset estimations may be sent along with the received OFDM symbols for FFT computation and generating a de-rotated signal output. The timing offset estimation may provide a reference point for dynamic tracking of timing for an OFDM signal and estimated based on an integral value associated with the OFDM signal.

    Maintaining repeater accuracy for satellite signal delivery systems

    公开(公告)号:US10903974B2

    公开(公告)日:2021-01-26

    申请号:US16521880

    申请日:2019-07-25

    Abstract: Systems and methods for maintaining synchronization of repeater networks with Global Positioning System (GPS) signals using phase locked loops (PLLs) and based on generation of predicted control words for controlling local oscillator frequencies is described. The predicted control words can be generated based on performing a linear fit of control words generated over a predetermined duration of time. Phase locked loops with additional false GPS pulse identification and GPS signal loss compensation circuitry can enforce a false pulse count threshold and/or an error threshold. The additional circuitry and prediction of control words can overcome errors in GPS receiver outputs and maintain accuracy of signal timings across single frequency networks using inexpensive local oscillators.

    SYSTEM AND METHODS TO RECLAIM UNUSED THROUGHPUT IN AN SDARS SYSTEM

    公开(公告)号:US20190123807A1

    公开(公告)日:2019-04-25

    申请号:US16168285

    申请日:2018-10-23

    Abstract: Systems, algorithms and methods for reclaiming unused portions of a satellite broadcast service's bandwidth for new services, utilizing higher performance coding techniques to yield better throughput, are presented. These systems, algorithms and methods achieve the reclaimed bandwidth in a way that is invisible to a legacy receiver, and that does not interfere with its reception of a legacy signal. In one embodiment, new data may be transmitted within a legacy transmission frame, for example within its cluster structure, using the same modulation and synchronization as used for the legacy data. The new data may be inserted into a channel or other subdivision at a head end. In another embodiment, one or more clusters or subdivisions with only new data may be transmitted, using the same modulation and synchronization as the legacy data clusters, but now employing a higher performing FEC and data interleaving structure on those clusters which contain only new data to yield an increase in available throughput. Finally, in a third embodiment, one or more clusters containing only new data may be transmitted, and in said one or more all new data clusters, different modulation and synchronization may be used then that of the legacy data clusters, thus employing a higher performing FEC and data interleaving structure than that of the legacy clusters. Various combinations of these approaches are also presented, as well as a set of novel receivers, or receiver configurations, to implement them and their combinations

    OVERLAY MODULATION TECHNIQUE OF COFDM SIGNALS BASED ON AMPLITUDE OFFSETS

    公开(公告)号:US20170230212A1

    公开(公告)日:2017-08-10

    申请号:US15271751

    申请日:2016-09-21

    Abstract: Systems and methods are presented for transmitting additional data over preexisting differential COFDM signals by changing the amplitude of the legacy data symbols. In exemplary embodiments of the present invention, additional data capacity can be achieved for a COFDM signal which is completely backwards compatible with existing legacy satellite broadcast communications systems. In exemplary embodiments of the present invention, additional information can be overlaid on a legacy COFDM signal by applying an amplitude offset to the legacy symbols. In exemplary embodiments of the present invention, special receiver processing can be implemented to extract this additional information, which can include performing channel equalization across frequency bins to isolate the amplitude modulated overlay signal. For example, at each FFT symbol time, average power across neighboring active data bins can be used to determine the localized power at the corresponding FFT bins, and a channel inversion can then, for example, be performed on the data bins to restore, as best as possible, the original transmitted symbol amplitude.

    NOISE POWER ESTIMATION IN DIGITAL COMMUNICATIONS SYSTEMS WITH FAST FADING CHANNELS
    27.
    发明申请
    NOISE POWER ESTIMATION IN DIGITAL COMMUNICATIONS SYSTEMS WITH FAST FADING CHANNELS 审中-公开
    数字通信系统噪声功率估计与快速衰减信道

    公开(公告)号:US20160028423A1

    公开(公告)日:2016-01-28

    申请号:US14774930

    申请日:2014-03-18

    CPC classification number: H04B1/10 H04L1/20 H04L1/206 H04L25/062

    Abstract: An accurate and fast method for estimation of noise power in digital communication systems is presented. Exemplary embodiments of the present invention do not rely upon the need for embedding reference sequences in the transmitted data. Accordingly, such exemplary embodiments are especially suited for tracking variations of noise power in digital communication systems with fast fading channels.

    Abstract translation: 提出了一种准确,快速的数字通信系统中噪声功率估计方法。 本发明的示例性实施例不依赖于在所发送的数据中嵌入参考序列的需要。 因此,这样的示例性实施例特别适用于跟踪具有快速衰落信道的数字通信系统中噪声功率的变化。

    Efficient, programmable and scalable low density parity check decoder
    28.
    发明授权
    Efficient, programmable and scalable low density parity check decoder 有权
    高效,可编程和可扩展的低密度奇偶校验解码器

    公开(公告)号:US09160366B2

    公开(公告)日:2015-10-13

    申请号:US14070000

    申请日:2013-11-01

    Abstract: Novel design of an LDPC decoder suitable for a range of code-block sizes and bit-rates, also suitable for both ASIC and FPGA implementations, is provided, in which the overhead associated with correction data sent along the transmission channel can be minimized. An LDPC decoder can be optimized for either eIRA based or general H matrices. An H parity matrix can be constructed and/or manipulated to arrange the bit-node message “columns” to facilitate mapping to MPB “columns” and corresponding access via LUT pointer tables to minimize processing cycles so as to: (i) minimize address conflicts within the same MPB that will take multiple access cycles to resolve; (ii) minimize splitting of bit-node messages across MPB “columns” that will take multiple access cycles to resolve; and (iii) balance the bit-node computations across all the MPB/LUT “columns” so that they will complete their computations at nearly the same time.

    Abstract translation: 提供了适用于一系列码块大小和比特率的LDPC解码器的新颖设计,也适用于ASIC和FPGA实现,其中与传输信道发送的校正数据相关联的开销可以最小化。 可以针对基于eIRA或一般H矩阵优化LDPC解码器。 可以构造和/或操纵H奇偶校验矩阵以排列比特节点消息“列”以便于映射到MPB“列”以及经由LUT指针表的对应访问以最小化处理周期,以便:(i)最小化地址冲突 在同一个MPB中,将采取多个访问周期来解决; (ii)最大限度地减少跨越将需要多个访问周期来解决的MPB“列”的位节点消息; 并且(iii)平衡所有MPB / LUT“列”上的位节点计算,使得它们将在几乎相同的时间完成它们的计算。

    Efficient implementation to perform iterative decoding with large iteration counts
    30.
    发明授权
    Efficient implementation to perform iterative decoding with large iteration counts 有权
    高效实现以大的迭代计数执行迭代解码

    公开(公告)号:US08910015B2

    公开(公告)日:2014-12-09

    申请号:US13690775

    申请日:2012-11-30

    CPC classification number: H03M13/6505 H03M13/05 H03M13/1105 H03M13/3746

    Abstract: Systems and methods are presented to improve the performance of a constant bit rate iterative decoder by providing elastic buffering, while utilizing a relatively simple decoder architecture capable of maintaining a fixed number of iterations of a lower value. An LDPC decoder can be designed, for example, to support less than the maximum possible number of iterations, and can, for example, be mated to elastic input and output buffers. If a given code block, or succession of code blocks, requires the maximum number of iterations for decoding, the decoder can, for example, run at such maximum number of iterations and the elastic input buffer can, for example, hold code blocks waiting to be processed so as to maintain a constant input rate. Alternatively, if one or more code blocks requires less than the nominal number of iterations, the output buffer can store those code blocks so as to preserve a constant output rate. It is emphasized that this abstract is provided to comply with the rules requiring an abstract, and is submitted with the understanding that it will not be used to interpret or limit the scope or the meaning of the claims.

    Abstract translation: 提出了系统和方法,以通过提供弹性缓冲来提高恒定比特率迭代解码器的性能,同时利用能够维持较低值的固定次数迭代的相对简单的解码器架构。 例如,LDPC解码器可以被设计为支持小于最大可能的迭代次数,并且可以例如与弹性输入和输出缓冲器配合。 如果给定代码块或连续的代码块需要用于解码的最大迭代次数,则解码器可以例如以这样的最大迭代次数运行,并且弹性输入缓冲器可以例如保持等待 进行处理以保持恒定的输入速率。 或者,如果一个或多个代码块需要小于标称的迭代次数,则输出缓冲器可以存储那些代码块,以便保持恒定的输出速率。 要强调的是,提供本摘要以符合要求抽象的规则,并提交了一项谅解,即不会将其用于解释或限制权利要求书的范围或含义。

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