公开(公告)号：US09800437B2

公开(公告)日：2017-10-24

申请号：US15071491

申请日：2016-03-16

申请人： Northrop Grumman Systems Corporation

发明人： Robert S. Kingery ,  Daniel N. Liu

IPC分类号： H03M13/00 ,  H04L25/03 ,  H03M13/27 ,  H03M13/39 ,  H03M13/41

CPC分类号： H04L25/03229 ,  H03M13/2771 ,  H03M13/2792 ,  H03M13/3905 ,  H03M13/3944 ,  H03M13/3955 ,  H03M13/3972 ,  H03M13/41 ,  H03M13/6331 ,  H04L25/03019 ,  H04L25/03171 ,  H04L25/03305 ,  H04L25/03318

摘要： An apparatus and method for optimizing the performance of satellite communication system receivers by using the Soft-Input Soft-Output (SISO) BCJR (Bahl, Cocke, Jelinek and Raviv) algorithm to detect a transmitted information sequence is disclosed. A Sliding Window technique is used with a plurality of reduced state sequence estimation (RSSE) equalizers to execute the BCJR algorithm in parallel. A serial data stream is converted into a plurality of data blocks using a serial-to-parallel converter. After processing in parallel by the equalizers, the output blocks are converted back to a serial data stream by a parallel-to-serial converter. A path history is determined using maximum likelihood (ML) path history calculation.

公开(公告)号：US20150172793A1

公开(公告)日：2015-06-18

申请号：US14409421

申请日：2013-07-23

申请人： Alcatel Lucent

发明人： Arnaud Dupas ,  Roger Boislaigue

IPC分类号： H04Q11/00

CPC分类号： H04Q11/0005 ,  H03M13/27 ,  H03M13/2703 ,  H03M13/275 ,  H03M13/2757 ,  H03M13/2771 ,  H03M13/2778 ,  H03M13/2782 ,  H03M13/6561 ,  H04L1/0071 ,  H04Q11/0003

摘要： Proposed is a bit-interleaver for an optical line terminal of an optical access network. The bit-interleaver contains a memory reader, that provides data streams at bit level to a space-time switch. The space-time switch reads within one input cycle up to N bit sets from the data streams. The switch switches within one writing cycle up to N bits onto up to its output ports, which provide respective output vectors. A number of N OR-function elements determine within the writing cycle respective single output bits. A number of N memory elements write within the one writing cycle a respective one of the output bits into a respective one of their bit sub-elements. A control unit that controls the reading of the data streams and also the switching of the bits by the switch. The control unit controls a choice of the writing addresses.

摘要翻译： 提出了用于光接入网络的光线路终端的位交织器。 位交织器包含一个存储器读取器，它将位数据流提供给时空交换机。 空时切换器在一个输入周期内读取数据流中最多N位的集合。 开关在一个写入周期内切换到最多N位，直到其输出端口，其提供相应的输出向量。 一些N个OR函数元件在写入周期内决定相应的单个输出位。 多个N个存储器元件在一个写入周期内将相应的一个输出位写入它们的位子元素中的相应一个。 控制单元控制数据流的读取以及开关切换位。 控制单元控制写地址的选择。

公开(公告)号：US09037939B2

公开(公告)日：2015-05-19

申请号：US14149379

申请日：2014-01-07

申请人： Sirius XM Radio Inc.

发明人： Carl Scarpa ,  Edward Schell

IPC分类号： G06F11/00 ,  H03M13/11 ,  H03M13/27 ,  H04B7/185 ,  H04L1/00

CPC分类号： H03M13/1105 ,  H03M13/1102 ,  H03M13/2732 ,  H03M13/2746 ,  H03M13/2771 ,  H03M13/2792 ,  H04B7/1858 ,  H04L1/0057 ,  H04L1/0071

摘要： Systems, methods and apparatus are described to interleave LDPC coded data for reception over a mobile communications channel, such as, for example, a satellite channel. In exemplary embodiments of the present invention, a method for channel interleaving includes segmenting a large LDPC code block into smaller codewords, randomly shuffling the code segments of each codeword and then convolutionally interleaving the randomly shuffled code words. In exemplary embodiments of the present invention, such random shuffling can guarantee that no two consecutive input code segments will be closer than a defined minimum number of code segments at the output of the shuffler. In exemplary embodiments of the present invention, by keeping data in, for example, manageable sub-sections, accurate SNR estimations, which are needed for the best possible LDPC decoding performance, can be facilitated based on, for example, iterative bit decisions.

公开(公告)号：US08874858B2

公开(公告)日：2014-10-28

申请号：US13157085

申请日：2011-06-09

申请人： Nur Engin

发明人： Nur Engin

IPC分类号： H03M13/27 ,  G06F12/00 ,  H03M13/00

CPC分类号： H03M13/2789 ,  H03M13/271 ,  H03M13/2725 ,  H03M13/2739 ,  H03M13/276 ,  H03M13/2764 ,  H03M13/2771 ,  H03M13/2775 ,  H03M13/6519 ,  H03M13/6525

摘要： A reconfigurable interleaver is provided, configured to produce a sequence of interleaved addresses, configurable for at least two different interleaving patterns. The reconfigurable interleaver comprises a plurality of reconfigurable counters. The number of values that the counters count is configurable as are their start values. The interleaver further comprises a plurality of memory in which the counters indicate memory positions so that values may be retrieved. Computational elements compute an interleaved sequence of addresses in dependency on the retrieved values. By reconfiguring the counters and possibly changing the content of the memories, the interleaver may be configured for a different interleaving pattern.

摘要翻译： 提供可重构交错器，其被配置为产生可配置用于至少两个不同交织模式的交错地址序列。 可重配置交织器包括多个可重配置计数器。 计数器计数的值的数量可以是其起始值。 交织器还包括多个存储器，其中计数器指示存储器位置，从而可以检索值。 计算元素根据检索到的值计算交织的地址序列。 通过重新配置计数器并且可能改变存储器的内容，交织器可以被配置为不同的交织模式。

公开(公告)号：US20140289592A1

公开(公告)日：2014-09-25

申请号：US14300734

申请日：2014-06-10

申请人： InterDigital Technology Corporation

发明人： Philip J. Pietraski ,  Gregory S. Sternberg

IPC分类号： H03M13/27 ,  H03M13/00

CPC分类号： H03M13/2771 ,  H03M13/005 ,  H03M13/2792 ,  H03M13/2957 ,  H03M13/6362 ,  H03M13/6381 ,  H04L1/0067

摘要： Detecting, avoiding and/or correcting problematic puncturing patterns in parity bit streams used when implementing punctured Turbo codes is achieved without having to avoid desirable code rates. This enables identification/avoidance of regions of relatively poor Turbo code performance. Forward error correction comprising Turbo coding and puncturing achieves a smooth functional relationship between any measure of performance and the effective coding rate resulting from combining the lower rate code generated by the Turbo encoder with puncturing of the parity bits. In one embodiment, methods to correct/avoid degradations due to Turbo coding are implemented by puncturing interactions when two or more stages of rate matching are employed.

摘要翻译： 检测，避免和/或纠正实现穿孔Turbo码时使用的奇偶校验比特流中有问题的打孔模式，而无需避免所需的代码率。 这使得能够识别/避免相对较差的Turbo码性能的区域。 包括Turbo编码和穿孔的前向纠错实现了任何性能测量与由Turbo编码器产生的较低速率码与奇偶校验位的打孔所产生的有效编码速率之间的平滑功能关系。 在一个实施例中，用于校正/避免由Turbo编码引起的劣化的方法通过采用两个或更多个速率匹配阶段时的穿孔交互实现。

公开(公告)号：US08595584B2

公开(公告)日：2013-11-26

申请号：US12990865

申请日：2008-05-19

申请人： Yuval Neeman ,  Guy Drory ,  Aviel Livay ,  Inbar Schori

发明人： Yuval Neeman ,  Guy Drory ,  Aviel Livay ,  Inbar Schori

IPC分类号： H03M13/00

CPC分类号： H03M13/2771 ,  H03M13/2739 ,  H03M13/2957 ,  H03M13/6525

摘要： A semiconductor device comprising processing logic. The processing logic is arranged to configure interleaver logic to re-order data symbols of a data stream according to a quadrature permutation polynomial function. The processing logic is further arranged to: divide a cyclic group of values defined by the QPP function into a set of subgroups, the set of subgroups being capable of being defined by a set of linear functions; derive inverse functions for the set of linear functions defining the subgroups; and configure the interleaver logic to load the data symbols of the data stream into a buffer at locations within the buffer corresponding to a cyclic group of values representative of the inverse function for the QPP function based on the inverse functions of the set of linear functions defining the subgroups.

摘要翻译： 一种包括处理逻辑的半导体器件。 处理逻辑被配置为配置交织器逻辑以根据正交置换多项式函数重新排序数据流的数据符号。 所述处理逻辑还被配置为：将由所述QPP功能定义的循环组划分成一组子组，所述一组子组能够由一组线性函数定义; 导出定义子组的一组线性函数的反函数; 并且配置交织器逻辑，以基于定义的线性函数集合的反函数将数据流的数据符号加载到缓冲器中，该缓冲器位于对应于表示QPP函数的反函数的循环数组的缓冲器内的位置 子组。

公开(公告)号：US08473829B2

公开(公告)日：2013-06-25

申请号：US12941178

申请日：2010-11-08

申请人： Tak K. Lee ,  Ba-Zhong Shen

发明人： Tak K. Lee ,  Ba-Zhong Shen

IPC分类号： H03M13/00

CPC分类号： H03M13/2771 ,  H03M13/276 ,  H03M13/2957 ,  H03M13/6561 ,  H04L1/005 ,  H04L1/0066

摘要： Address generation for contention-free memory mappings of turbo codes with ARP (almost regular permutation) interleaves. Anticipatory address generation is employed using an index function , that is based on an address mapping , which corresponds to an interleave inverse order of decoding processing (π−1). In accordance with parallel turbo decoding processing, instead of performing the natural order phase decoding processing by accessing data elements from memory bank locations sequentially, the accessing of addresses is performed based on the index function , that is based on an mapping and the interleave (π) employed within the turbo coding. In other words, the accessing data elements from memory bank locations is not sequential for natural order phase decoding processing. The index function also allows for the interleave (π) order phase decoding processing to be performed by accessing data elements from memory bank locations sequentially.

摘要翻译： 具有ARP（几乎规则排列）交织的turbo码的无竞争内存映射的地址生成。 使用基于地址映射的索引函数来采用预期地址生成，该地址映射对应于解码处理（pi-1）的交织逆序。 根据并行turbo解码处理，代替通过依次从存储体单元访问数据元素来执行自然次序相位解码处理，基于索引函数执行地址的访问，该索引函数是基于映射和交织（pi ）。 换句话说，来自存储体位置的访问数据元素对于自然顺序相位解码处理不是顺序的。 索引函数还允许通过从存储体单元顺序访问数据元素来执行交织（pi）阶相位解码处理。

公开(公告)号：US08448033B2

公开(公告)日：2013-05-21

申请号：US12955709

申请日：2010-11-29

申请人： Cheng-Chi Wong ,  Hsi-Chia Chang

发明人： Cheng-Chi Wong ,  Hsi-Chia Chang

IPC分类号： G06F11/00

CPC分类号： H03M13/2775 ,  H03M13/2739 ,  H03M13/2753 ,  H03M13/2771 ,  H03M13/2957 ,  H03M13/2978 ,  H03M13/3905 ,  H03M13/3972

摘要： An error correction code encoder is provided. A first encoder encodes input information bits and generates first parity check bits. An interleaver interleaves the input information bits and generates permuted information bits. A second encoder encodes the permuted information bits and generates second parity check bits. The interleaver interleaves the input information bits in a window-wise manner so that the input information bits are divided into input information bit windows before being interleaved, and permuted information bit windows having the permuted information bits are generated thereafter. When the input information bit windows are grouped into groups according to different window index characteristics, the window index of each permuted information bit window has the same characteristic as the corresponding input information bit window interleaved therefrom.

摘要翻译： 提供纠错码编码器。 第一编码器对输入信息比特进行编码并产生第一奇偶校验位。 交织器对输入信息比特进行交织并产生置换的信息比特。 第二编码器对置换的信息位进行编码，并产生第二奇偶校验位。 交织器以窗口方式对输入信息比特进行交织，使得输入信息比特在被交织之前被划分为输入信息比特窗口，此后产生具有置换信息比特的置换信息比特窗口。 当输入信息比特窗口根据不同窗口索引特性被分组成组时，每个置换的信息比特窗口的窗口索引具有与其交错的对应的输入信息比特窗口的特征相同的特征。

公开(公告)号：US08332701B2

公开(公告)日：2012-12-11

申请号：US12647394

申请日：2009-12-25

申请人： Shuenn-Gi Lee ,  Chung-Hsuan Wang ,  Wern-Ho Sheen

发明人： Shuenn-Gi Lee ,  Chung-Hsuan Wang ,  Wern-Ho Sheen

IPC分类号： G06F11/00

CPC分类号： H03M13/2771 ,  H03M13/2739 ,  H03M13/2764 ,  H03M13/2957 ,  H03M13/3972 ,  H03M13/6525 ,  H03M13/6561

摘要： An address generation apparatus for a quadratic permutation polynomial (QPP) interleaver is provided. It comprises a basic recursive unit, and L recursive units represented by first recursive unit up to Lth recursive units. The apparatus inputs a plurality of configurable parameters according to a QPP function Π(i)=(f1i+f2i2) mod k, generates a plurality of interleaver addresses in serial via the basic recursive unit, and generates L groups of corresponding interleaver addresses via the first up to the Lth recursive units, wherein Π(i) is the i-th interleaver address generated by the apparatus, f1 and f2 are QPP coefficients, and k is information block length of an input sequence, 0≦i≦k−1.

摘要翻译： 提供了一种用于二次置换多项式（QPP）交织器的地址生成装置。 它包括一个基本递归单元，和由递归单位表示的L个递归单元，直到第L个递归单元。 该设备根据QPP功能＆Pgr输入多个可配置参数;（i）=（f1i + f2i2）mod k，经由基本递归单元串行生成多个交织器地址，并通过以下方式生成L组对应的交织器地址 第一个到第L个递归单元，其中＆Pgr;（i）是由装置生成的第i个交织器地址，f1和f2是QPP系数，k是输入序列的信息块长度，0＆nlE; i＆nlE; k -1。

公开(公告)号：US08321725B2

公开(公告)日：2012-11-27

申请号：US11980917

申请日：2007-10-31

申请人： Mustafa Eroz ,  A. Roger Hammons, Jr. ,  Feng-Wen Sun

发明人： Mustafa Eroz ,  A. Roger Hammons, Jr. ,  Feng-Wen Sun

IPC分类号： H03M13/27

CPC分类号： H03M13/271 ,  H03M13/2735 ,  H03M13/2746 ,  H03M13/276 ,  H03M13/2767 ,  H03M13/2771 ,  H03M13/2789 ,  H03M13/2957

摘要： A method of interleaving blocks of indexed data of varying length is disclosed. The method includes the steps of: providing a set of basic Interleavers comprising a family of one or more permutations of the indexed data and having a variable length; selecting one of the basic Interleavers based upon a desired Interleaver length L; and adapting the selected basic Interleaver to produce an Interleaver having the desired Interleaver length L.

摘要翻译： 公开了一种交织具有不同长度的索引数据块的方法。 该方法包括以下步骤：提供一组基本交错器，其包括索引数据的一个或多个排列的族，并具有可变长度; 基于所需的交织器长度L选择基本交织器之一; 并且使所选择的基本交织器适配以产生具有期望的交织器长度L的交织器。