公开(公告)号：US08975730B2

公开(公告)日：2015-03-10

申请号：US13622573

申请日：2012-09-19

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics SA

Inventor： Didier Dutartre ,  Michel Marty ,  Sebastien Jouan

IPC: H01L29/06 ,  H01L21/768 ,  H01L21/762

CPC classification number: H01L21/76898 ,  H01L21/76251

Abstract: A device and corresponding fabrication method includes a vertical stack having an intermediate layer between a lower region and an upper region. The intermediate layer is extended by a protection layer. The vertical stack has a free lateral face on which the lower region, the upper region and the protection layer are exposed.

Abstract translation: 一种器件和相应的制造方法包括在下部区域和上部区域之间具有中间层的垂直堆叠。 中间层由保护层延伸。 垂直堆叠具有自由侧面，下部区域，上部区域和保护层暴露在该侧面上。