公开(公告)号：US08860186B2

公开(公告)日：2014-10-14

申请号：US13766925

申请日：2013-02-14

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Mohamed Bouchoucha ,  Laurent-Luc Chapelon

IPC: H01L29/40 ,  H01L21/768 ,  H01L23/48 ,  H01L23/522

CPC classification number: H01L21/768 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/522 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05 ,  H01L2224/05548 ,  H01L2224/13 ,  H01L2224/13024 ,  H01L2224/16146 ,  H01L2924/13091 ,  H01L2924/00

Abstract: A method for forming an integrated circuit including the steps of: forming electronic components on a first surface of a substrate; forming a stack of interconnection levels on the first surface, each interconnection level including conductive tracks separated by an insulating material; forming at least one hole from a second surface of the substrate, opposite to the first surface, the hole stopping on one of the conductive tracks; depositing, on the walls and the bottom of the hole, a conductive layer and filling the remaining space with a filling material; and forming, in an interconnection level or at the surface of the interconnection stack, and opposite to said at least one hole, at least one region of a material having a modulus of elasticity greater than 50 GPa and an elongation at break greater than 20%, insulated from the conductive tracks.

Abstract translation: 一种用于形成集成电路的方法，包括以下步骤：在基板的第一表面上形成电子部件; 在所述第一表面上形成一叠互连层，每个互连层包括由绝缘材料隔开的导电轨道; 从所述基板的与所述第一表面相对的第二表面形成至少一个孔，所述孔在所述导电轨道中的一个上停止; 在孔的壁和底部上沉积导电层并用填充材料填充剩余的空间; 以及在所述互连叠层的互连层或所述表面上形成并与所述至少一个孔相对的材料的至少一个区域具有大于50GPa的弹性模量和断裂伸长率大于20％ ，与导电轨道绝缘。