公开(公告)号：US11600601B2

公开(公告)日：2023-03-07

申请号：US17382169

申请日：2021-07-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Aenee Jang

IPC: H01L23/00 ,  H01L25/065 ,  H01L23/48

Abstract: A semiconductor package comprising a first semiconductor chip and a second semiconductor chip disposed on the first semiconductor chip, wherein the first semiconductor chip includes a first semiconductor body, an upper pad structure, and a first through-electrode penetrating the first semiconductor body and electrically connected to the upper pad structure, and the second semiconductor chip includes a second semiconductor body, a lower bonding pad, and an internal circuit structure including a circuit element, internal circuit wirings, and a connection pad pattern disposed on the same level as the lower bonding pad, the upper pad structure includes upper bonding pads and connection wirings, the upper bonding pads are disposed at positions corresponding to the lower bonding pad and the connection pad pattern, and the internal circuit structure is electrically connected to the first through-electrode through at least one of the upper bonding pads and the connection wirings.

公开(公告)号：US11581248B2

公开(公告)日：2023-02-14

申请号：US17224549

申请日：2021-04-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Aenee Jang

IPC: H01L23/498 ,  H01L23/31 ,  H01L23/538 ,  H01L23/00 ,  H01L25/18

Abstract: A semiconductor package includes a base substrate; an interposer substrate including a semiconductor substrate having a first surface facing the base substrate and a second surface, opposing the first surface, and a passivation layer on at least a portion of the first surface; a plurality of connection bumps between the base substrate and the interposer substrate; an underfill resin in a space between the base substrate and the interposer substrate; and a first semiconductor chip and a second semiconductor chip on the interposer substrate. The interposer substrate has a first region, in which the plurality of connection bumps are included, and a second region and a third region adjacent a periphery of the first region, and the passivation layer is in the second region and includes a first embossed pattern in the second region.

公开(公告)号：US20220077039A1

公开(公告)日：2022-03-10

申请号：US17224549

申请日：2021-04-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Aenee Jang

IPC: H01L23/498 ,  H01L25/18 ,  H01L23/31 ,  H01L23/538 ,  H01L23/00

Abstract: A semiconductor package includes a base substrate; an interposer substrate including a semiconductor substrate having a first surface facing the base substrate and a second surface, opposing the first surface, and a passivation layer on at least a portion of the first surface; a plurality of connection bumps between the base substrate and the interposer substrate; an underfill resin in a space between the base substrate and the interposer substrate; and a first semiconductor chip and a second semiconductor chip on the interposer substrate. The interposer substrate has a first region, in which the plurality of connection bumps are included, and a second region and a third region adjacent a periphery of the first region, and the passivation layer is in the second region and includes a first embossed pattern in the second region.