Image sensor and imaging device including the same

    公开(公告)号:US11503229B2

    公开(公告)日:2022-11-15

    申请号:US17038347

    申请日:2020-09-30

    Abstract: An imaging device includes a pixel array with a plurality of pixels each configured to generate a reset signal and an image signal, a sampling circuit including a plurality of samplers connected to column lines, where each sampler generates a first comparison signal by comparing the reset signal with a ramp signal and generates a second comparison signal by comparing the image signal with the ramp signal. An ADC converts each of the first and second comparison signals into a digital signal. Each sampler performs an auto-zero operation for initializing itself before performing the comparing with respect to the reset signal in a first mode, and performs a respective auto-zero operation before performing the comparing for each of the reset signal and the image signal in a second mode.

    Image sensor, address decoder including clock tree, and image processing system including the image sensor

    公开(公告)号:US10992894B2

    公开(公告)日:2021-04-27

    申请号:US16838483

    申请日:2020-04-02

    Abstract: An image sensor includes a pixel array including pixels that are arranged in a matrix and respectively generate pixel signals, a row driver to drive the plurality of pixels row by row, a timing generator to generate a clock signal and address signals, a column driver to generate a plurality of column selection signals sequentially activated in response to the clock signal and the address signals, and a column array to receive the pixel signals through a plurality of column lines, perform an analog-to-digital conversion on the pixel signals, and sequentially output pixel data values through an output buffer. The column driver may include a clock tree including first delay elements and second delay elements to generate a plurality of delay clock signals, and a decoding circuit to generate the plurality of column selection signals.

    IMAGE SENSOR HAVING REDUCED PARASITIC CAPACITANCE

    公开(公告)号:US20210120200A1

    公开(公告)日:2021-04-22

    申请号:US16890422

    申请日:2020-06-02

    Abstract: An image sensor, including a pixel array including a plurality of pixels connected to row lines extending in a first direction and column lines extending in a second direction intersecting the first direction; a ramp voltage generator configured to output a ramp voltage; a sampling circuit including a plurality of comparators, each comparator of the plurality of comparators having a first input terminal connected to a column of the column lines and a second input terminal configured to receive the ramp voltage; and an analog-to-digital converter configured to convert an output of the plurality of comparators to a digital signal, wherein the plurality of comparators include a first comparator connected to a first column line, and a second comparator connected to a second column line adjacent to the first column line in the first direction, wherein each of the first comparator and the second comparator includes a first transistor and a second transistor disposed sequentially in the second direction, and wherein a gap between the first transistor of the first comparator and the second transistor of the first comparator is different from a gap between the first transistor of the second comparator and the second transistor of the second comparator.

    Image sensors including shielding structures

    公开(公告)号:US10313616B2

    公开(公告)日:2019-06-04

    申请号:US15434605

    申请日:2017-02-16

    Abstract: An image sensor includes first pixels and second pixels arranged in alternating order along a first direction, first output lines extending in a second direction that is perpendicular to the first direction and respectively connected to the first pixels, second output lines extending in the second direction and respectively connected to the second pixels, first analog circuit blocks and second analog circuit blocks arranged in alternating order along the first direction, and shielding structures disposed each between adjacent ones of the first and second analog circuit blocks. Each of the first analog circuit blocks includes a plurality of first analog circuits respectively connected to the first output lines. Each of the second analog circuit blocks includes a plurality of second analog circuits respectively connected to the second output lines.

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