摘要:
An image sensor includes a pixel array including a first pixel and a second pixel which are connected to a first column line, and a row driver configured to control a read operation of the second pixel. A voltage of the first column line is determined based on a higher voltage among a voltage of a floating diffusion node of the first pixel and a voltage of a floating diffusion node of the second pixel during the read operation of the second pixel.
摘要:
An image sensor compensates for noise. The image sensor includes a pixel array that includes a common monitor output line, a first monitoring pixel outputting a first monitoring signal, a second monitoring pixel outputting a second monitoring signal, and an active pixel configured to output a sensing signal based on an incident light. The image circuit also includes a binning circuit that receives the first and second monitoring signals through the common monitor output line and generates an average monitoring signal by performing binning on the first and second monitoring signals, and an analog-to-digital converter that detects an alternating current (AC) component of the average monitoring signal and couples the sampled AC component of the average monitoring signal to the sensing signal, thereby compensating for noise.
摘要:
An analog to digital converting circuit includes a correlated double sampling circuit (CDS) that compares a pixel signal with a ramp signal, and outputs a comparison signal, a timing amplifier that increases an active time of the comparison signal “N” times, and outputs an extended signal, wherein the “N” is a positive integer, and a counter that outputs a digital signal corresponding to the pixel signal in response to the extended signal and a first clock signal.
摘要:
An electronic circuit includes a unit pixel, a first clamp circuit, and a second clamp circuit. The unit pixel outputs a voltage having an output voltage level at a first output voltage level in a first time interval and at a second output voltage level in a second time interval different from the first time interval. The first clamp circuit is configured to clamp the output voltage level from the unit pixel to a first voltage level responsive to the first output voltage level being not greater than the first voltage level in the first time interval. The second clamp circuit is configured to clamp the output voltage level from the unit pixel to a second voltage level responsive to the second output voltage level being not greater than the second voltage level in the second time interval.
摘要:
A method and apparatus are provided for handing over from a Long Term Evolution (LTE) network to a Circuit Switching (CS) network by a call manager in a wireless communication system. The method includes receiving, from an Enhanced Node B (ENB) of the LTE network, a handover required message for a Packet Switching (PS) to CS handover from the LTE network to the CS network, when the PS to CS handover is decided based on measurement reports of a User Equipment (UE); sending, to a Mobile Switching Center (MSC) of the CS network, a PS to CS handover request message including an International mobile subscriber identity (IMSI) for identifying the UE and a target IDentifier (ID) for a target cell of the CS network; receiving a PS to CS handover response message from the MSC; and sending, to the UE via the ENB, a handover command message.
摘要:
An image sensor includes multiple counters and a counter controller. Each counter of the multiple counters is configured to perform counting of a comparison result signal and to generate a count result, the comparison result signal being obtained by comparing a ramp signal and a pixel signal of a column of multiple columns. The counter controller is configured to generate and transmit a counter clock signal and (n−1) delay clock signals to the counters, respectively, “n” being a natural number equal to or greater than two. Each delay clock signal of the (n−1) delay clock signals is obtained by delaying the counter clock signal by a corresponding offset code.
摘要:
An analog-digital converter includes a count code generator to receive a code generation clock signal from a clock signal generator and to output a count code according to the code generation clock signal, a latch to latch the count code, an operating circuit to generate a count value of the count code and to output a digital signal based on the count value, and a transfer controller to transfer the count code from the latch to the operating circuit. The transfer controller determines whether to transfer the count code according to a logic level of a count enable clock signal generated from the clock signal generator.
摘要:
Disclosed is a bandgap reference circuit, which includes a first current generator that generates a first current proportional to a temperature, a second current generator that outputs a second current obtained by mirroring the first current to a first node at which a reference voltage is formed, a first resistor that is connected with the first node and is supplied with the second current, and a first bipolar junction transistor (BJT) that includes an emitter node connected with the first resistor, a base node supplied with a first power, and a collector node supplied with a second power different from the first power.
摘要:
An analog to digital converting circuit includes a correlated double sampling circuit (CDS) that compares a pixel signal with a ramp signal, and outputs a comparison signal, a timing amplifier that increases an active time of the comparison signal “N” times, and outputs an extended signal, wherein the “N” is a positive integer, and a counter that outputs a digital signal corresponding to the pixel signal in response to the extended signal and a first clock signal.
摘要:
An analog-digital converter includes a count code generator to receive a code generation clock signal from a clock signal generator and to output a count code according to the code generation clock signal, a latch to latch the count code, an operating circuit to generate a count value of the count code and to output a digital signal based on the count value, and a transfer controller to transfer the count code from the latch to the operating circuit. The transfer controller determines whether to transfer the count code according to a logic level of a count enable clock signal generated from the clock signal generator.