Abstract:
A content addressable memory (CAM) device. The CAM device is a synchronous device that may perform all of the following operations all in one clock cycle: (1) receive comparand data from a comparand bus; (2) receive an instruction from an instruction bus instructing the CAM device to compare the comparand data with a first group of CAM cells in a CAM array; (3) perform the comparison of the comparand data with the first group of CAM cells; (4) generate a match address for a location in the CAM array that stores data matching the comparand data; (5) access data stored in a second group of the CAM cells in the CAM array, wherein the second group of CAM cells may store data associated with the matched location; and (6) output to an output bus the match address, the data stored in the second group of CAM cells, and/or status information corresponding to the matched address or the second group of CAM cells. The status information may include a match flag, multiple match flag, full flag, skip bit, empty bit, or a device identification for the CAM device. The CAM array may also include ternary CAM cells that are individually maskable so as to effectively store either a logic one, logic zero, or a don't care state for compare operations.
Abstract:
A CAM device that allows defective rows in one CAM block to be functionally replaced by spare rows from any CAM block in the device. In some embodiments, the CAM device includes a main address decoder, a plurality of CAM blocks, a corresponding plurality of spare address decoders, and a block select circuit. In one embodiment, each CAM block includes a main CAM array having a plurality of rows of CAM cells each coupled to a corresponding word line, and a spare row of CAM cells coupled to a spare word line. Each spare row may be used to functionally replace a defective row in the same CAM block or in any other CAM block by programming the address of the defective row into the corresponding spare address decoder. During subsequent read or write operations, an input address is compared with the programmed addresses stored in the spare address decoders. If there is match, thereby indicating that the selected row is defective and has been replaced, the address decoder storing the matching programmed address enables the spare row in the corresponding CAM block, and the block select circuit enables the corresponding CAM block for the operation, so that the read or write operation accesses the spare row instead of the defective row. If there is not a match, the spare address decoder does not enable the corresponding spare word line, and the block select circuit enables the CAM block identified by the input address for the operation.
Abstract:
Match line control circuits are used to selectively charge corresponding match lines in response to the valid bits. If the valid bit is asserted, thereby indicating the valid data is stored in the CAM row, the match line control circuit pre-charges the match line to enable the match line to be responsive to compare operation between a comparand word and data stored in the row. If the valid bit is de-asserted, thereby indicating that any data stored in the row is invalid, the match line control circuit disables the match line by forcing a mismatch condition between the comparand word and data stored in the row. In one embodiment, the match line control circuit includes a pull-up transistor coupled between the match line and a supply voltage and having a gate responsive to the valid bit. In other embodiments, the match line control circuit further includes a pull-down transistor coupled between the match line and a supply voltage and having a gate responsive to a complement of the valid bit.
Abstract:
A ternary content addressable memory (CAM) cell. For one embodiment, the ternary CAM cell includes a first memory cell, a compare circuit, a second memory cell and a mask circuit. The first memory cell is coupled to a first pair of bit lines that carries data to and from the first memory cell. The compare circuit receives comparand data on a pair of compare signal lines, and compares the comparand data with the data stored in the first memory cell. The compare circuit includes a pair of transistors and a match transistor. The pair of transistors receives the comparand data on the compare signal lines and also receives the data stored in the first memory cell. The match transistor determines the state of a match line. The second memory cell stores mask data that may mask the comparison result such that it does not affect the logical state of the match line.
Abstract:
A method and apparatus for cascading content addressable memory (CAM) devices is disclosed. The method and apparatus may be particularly useful when depth cascading CAM devices that operate in a flow-through mode. In the flow-through mode, a compare instruction may be simultaneously provided to each CAM device in the cascade, and the match address, data stored at the matched location, or other status information may then be output to a common output data bus by the highest priority matching CAM device in the same cycle that the instruction is provided to the CAM devices. Each CAM device may have a cascade input and a cascade output to perform the cascade function. The cascade output of a higher priority CAM device may be connected to the cascade input of the next lower priority CAM device. The higher priority CAM device may assert a cascade signal on its cascade output at a predetermined time after receiving an input signal (e.g., a clock signal). Asserting the cascade signal may indicate that the higher priority CAM device has completed the compare instruction. When the lower priority CAM device detects that the cascade signal has been asserted on its cascade input, the lower priority CAM device may sample the match flag of the higher priority CAM device to determine if the lower priority CAM device may output its data to the common output data bus.
Abstract:
The proposed technology includes ophthalmic apparatuses and systems that allow transmission of a digital slit-lamp output (both of the visible light as well as of infra-red wavelength) over the web in “real-time” alongside face-to-face audio-visual communication between the various parties. The digital output of the camera will be in a format that is compatible with direct transmission over the web. This allows a person(s) at the remote site to see the slit-lamp imagery as if the remote examiner(s) were on site in the presence of the patient and simultaneously video-chat with the operator of the microscope to provide tele-consultation. The features also facilitate collaborative care between several providers, as well as patient representative(s), by enhancing the audio-visual communication between parties with the actual slit lamp imagery of the patient in real time.
Abstract:
A content addressable memory (CAM) device having any number of rows, each of the rows including a match line connected to a plurality of CAM cells, a match line detector circuit, and an incremental match line charge circuit. The detector circuit generates a feedback signal based on a detected match line voltage. The charge circuit partially pre-charges the match line to an intermediate voltage during a pre-charge phase of a compare operation, and then selectively charges the match line higher towards a supply voltage in response to the feedback signal.
Abstract:
A method and system to optimally route telephone calls between shared service centers is presented. Using a combination of service tiers, Agent Directory, Instant Messaging (IM), and Voice over Internet Protocol (VoIP) provides optimal routing of incoming calls for assistance. The method utilizes different protocols during normal operations, transitional operations, and emergency operations, and addresses Shared Service Center (SSC) planning and management.
Abstract:
A search system for detecting whether one or more overlapping sequences of input characters match a regular expression including a prefix string preceding an intermediate expression having a quantified number m of characters belonging to a specified character class is disclosed. The search system includes a CAM array for storing the regular expression, a shift register for counting sequences of input characters that match the character class, and a control circuit that enables the shift register in response to a prefix match and increments the shift register in response to character class matches.
Abstract:
A job searching and matching system and method is disclosed that gathers job seeker information in the form of job seeker parameters from one or more job seekers, gathers job information in the form of job parameters from prospective employers and/or recruiters, correlates the information with past job seeker behavior, parameters and behavior from other job seekers, and job parameters and, in response to a job seeker's query, provides matching job results based on common parameters between the job seeker and jobs along with suggested alternative jobs based on the co-relationships. In addition, the system correlates employer/recruiter behavior information with past employer/recruiter behavior, parameters and information concerning other job seekers, which are candidates to the employer, and resume parameters, and, in response to a Employer's query, provides matching job seeker results based on common parameters between the job seeker resumes and jobs along with suggested alternative job seeker candidates based on the identified co-relationships.